Search

Switching lattices formed by four-terminal switches are introduced as dense rectangular structures to implement Boolean logic functions. It is shown in literature that switching lattices offer a significant area advantage in terms of the number of switches over the conventional CMOS implementations. Although the computing potential of switching lattices has been well justified, the same thing cannot be said for their physical implementation. There have been conceptual ideas for the technology development, but no concrete and directly applicable technology has been proposed yet. In this study, we show that switching lattices can be implemented using the CMOS technology. For this purpose, we propose two different four-terminal switch structures with square and H shaped gates. We construct these structures in three-dimensional technology computer-aided design (TCAD) environment satisfying the design rules of the TSMC 65nm CMOS process and perform simulations. We develop Level 3 DC and AC models of the switches in LTspice environment using the TCAD simulation data. As an experiment, we realize logic functions with the developed models using static and dynamic logic solutions. Experimental results show that switching lattices occupy much less layout area and have competitive delay and power consumption values when compared to the conventional CMOS implementations

Bu çalışmada kaotik Rössler diferansiyel denklem kümesinin elektronik gerçeklemesi için memristör tabanlı yeni bir analog devre önerilmştir. Kaotik faz portreleri ve çatallanma diyagramları için matematiksel analizler ve SPICE simülasyonları yapılmışır. Önerilen sistem ticari olarak piyasada bulunan aktif ve pasif elemanlar kullanılarak bord üzerinde gerçeklenmiş ve deneysel çalışma yürütülmüştür. Elde edilen deneysel sonuçlar, matematiksel analizler ve simülasyon sonuçları ile uyumludur. İhtiyaç duyulan memristans karakteristiğini sağlayacak olan bir memristans simülatörü devresi önerilmiş, ve ona ait non-lineer dinamikler frekansa bağlı histeresis eğrileri incelenerek memristif yapısı doğrulanmıştır.

Purpose In this work, a true random number generator is designed by sampling the double-scroll analog continuous-time chaotic circuit signals. Methodology A Chua circuit based on memristance simulator is designed to obtain a non-linear term for a chaotic dynamic system. It is implemented on the board by using commercially available integrated circuits and passive elements. A low precision ADC which is commonly found in the market is used to sample the chaotic signals. The mathematical analysis of the chaotic circuit is verified by experimental results. Originality It is aimed to be one of the pioneering studies (including low precision ADC) in the literature on the implementation of memristive chaotic random number generators. Findings Two new methods are proposed for post-processing and creating random bit array using XOR operator and J-K flip flop. The bit stream obtained by a full-hardware implementation successfully passed the NIST-800-22 test. In this respect, the availability of the memristance simulator circuit, memristive chaotic double-scroll attractor, proposed random bit algorithm and the randomness of the memristive analog continuous-time chaotic true number generator were also verified.

Switching lattices, consisting of four-terminal switches, present an alternative structure for the realization of Boolean logic functions. Although promising algorithms have been introduced to find a realization of a logic function using a switching lattice with the fewest number of four-terminal switches, the delay of a switching lattice has not been examined yet. In this article, we generate a switching lattice using a recently proposed CMOS-compatible four-terminal device model and formulate the delay of a path in a switching lattice. It is observed that the delay of a design realizing a logic function on a switching lattice heavily depends on the number of four-terminal switches in the critical path. With this motivation, we introduce optimization algorithms, called PHAEDRA and TROADES, which can find the realization of a logic function on a switching lattice with the fewest number of switches under a delay constraint given in terms of the number of switches in the critical path. While PHAEDRA is a dichotomic search algorithm that can obtain solutions with a small number of switches on small size logic functions, TROADES is a divide-and-conquer method that can find a solution using less computational effort and can easily handle larger size logic functions with respect to PHAEDRA. The experimental results show that the proposed algorithms can reduce the delay of a lattice realization of a logic function significantly at a cost of an increase in the number of switches. They can explore alternative lattice realizations of a logic function by changing the delay constraint, enabling a designer to choose the one that fits best in an application.

In this work, a CBTA-based universal mutator circuit is proposed for the realization of memcapacitor and meminductor elements. Proposed mutator circuit contains only one CBTA element, one memristor and one capacitor. It is suitable to transform a grounded memristor to a floating memcapacitor or meminductor. SPICE simulation by using a CBTA designed with 0.18 μm level-7 TSMC CMOS transistors was performed to show the accuracy of the proposed circuit and as a result, frequency dependent hysteresis loops are obtained.

Chaos which is a complex, nonlinear and deterministic behavior have many fields of applications. This theory, which Lorenz describes with a simple mathematical model, has become a very important issue in the field of nonlinear circuits and systems. The discovery of the existence of chaos has opened up many different developments. One of these developments is to recognize that secure communication systems can be implemented with these systems by deriving from the sensitivity of chaotic systems to initial conditions. In this paper, a circuit based on Lorenz equations is synchronized for secure communication. The Lorenz circuit is adapted to two different synchronization methods. The synchronization circuits are analyzed mathematically in MATLAB, and the simulated in PSPICE. A secure communication system has been tested for both methods. The system results are compared.

Research on organic field effect transistors (OFETs) have been dramatically increased in the last decade, considering their lightweight and flexible structure as well as their practical and low-cost production. Building compact models and parameter extraction methods have also a critical importance in extensively using OFETs in electronic systems. In this paper, we propose a hybrid artificial bee colony algorithm as a parameter extraction tool and we compare it with purely mathematical and genetic algorithm-based parameter extraction methods. We apply these methods to a well-known OFET compact model for two different transistors, both having pentacene as organic semiconductor. First transistor (T1) is available in literature and the other one (T2) is fabricated in our laboratory. The proposed approach shows a good agreement with the experimental data of T1 with normalized RMS error (NRMSE) of 0.26%. However, it is 1.83% for T2 due to lack of measurements. If the shape of the data was same, the parameter extraction approaches would be expected to perform more successfully for both OFETs as well. Results are tabulated and performances of the methods are compared in the paper.

In this study, a mobile robot carrying an on board camera is designed and implemented, which can be controlled remotely with wireless technology. Android operating system based tablet computers (controller) control mobile robot remotely and one android interface program is designed for remote control. Mobile robot is a microcontroller based embedded system and its hardware works on Linux operating system. Mobile robot and controller communicate with Wi-Fi (Wireless Fidelity) communication (socket communication). Mobile robot's camera takes video continuously and sends it to controller screen. These video contents are examined by the controller user; speed and direction information are entered from touch screen and these information are sent to mobile robot. In this manner, mobile robot movement is provided. Mobile robot motion is handled by direct current (DC) motors controlling and it is achieved with Pulse Width Modulation (PWM) method. System consists of two interrelated systems. One interrelated system is mobile robot part and the other is controller part. Mobile robot works as a server and controller works as a client. Observed video, which are taking from on board web camera, send from server to client wirelessly. Client takes video and shows it on screen. User can control the mobile robot by setting direction and speed from android tablet. Entered information sent to server and server sets motion parameters by using this information. Real-time video transportation is achieved with Motion Joint Photographic Experts Group (MJPEG) on Linux operating system. Because of the system performance, captured video is not saved. In client side (controller), speed is arranged 0 to 100 and for motion, user can set direction to left, right and direct. On controller application screen, user can see entered speed and direction values by the animated images.

Minaei, Shahram (Dogus Author) The aim of this paper is proposing an alternative method to Gorski-Popiel Technique in realization of synthetic transformers. A new synthetic floating transformer (FT) circuit is also given. The proposed synthetic transformer circuit uses two current backward transconductance amplifiers (CBTAs), three resistors, and two grounded capacitors. The primary selfinductance, the secondary self-inductance, and the mutual inductance can be independently controlled and can be tuned electronically by changing the biasing current of the employed CBTAs. It has a good sensitivity performance with respect to tracking errors. A band-pass filter is also realized to test the performance of the proposed synthetic transformer circuit. The validity of the proposed synthetic transformer circuit is demonstrated by PSPICE simulations and experimental results.

WOS: 000425994300007, In this paper, a new active-C filter realizing the general nth-order low-pass voltage transfer functions using n voltage differencing gain amplifiers (VDGAs) is presented. In this realization minimum number of equal-valued grounded capacitors and n active elements are used. Due to the adjustability of the transconductance of the VDGA with current, different gains can be realized using the same building block and a simple filter structure can be created. The filter which is composed of VDGA building blocks is suitable for integration and advantageous in terms of eliminating parasitic effects because all capacitors are grounded and the filter structure has no resistors. All simulations are performed on SPICE and the accuracy of this method is validated experimentally with commercially available products upon on-board circuit.

WOS: 000255999900002, A novel current controllable floating or grounded inductor simulator circuit with minimum elements is proposed. The circuit uses two dual output- second generation current controlled conveyors (DO-CCCIIs) with parasitic resistance at terminal X and one grounded capacitor externally connected. Proposed circuit is suitable for fully integrated circuit design. Analysis and simulation results are included.

With the recent advances in memristors as a potential building block for future hardware, it becomes an important and timely topic to study on memristor modelling. Memristor models are important for designers to exhibit memristor behavior since memristor is not yet available in market. An ideal memristor behavior has been remodel with Generalized Regression Neural Network (GRNN) and presented in this paper. Mathematical equations are used with a set of given memristor process parameters such as R ON , R OFF , thickness of TiO 2 , and instantaneous memristor behaviour is modelled. The behavior of this model is in agreement with the calculations of HP Lab's and Joglekar's SPICE model.

The authors propose two new configurations suitable for high-order filter response. It is possible to realize the most general nth-order current-mode transfer function using these configurations, involving a single or two current-differencing buffered amplifiers (CDBAs) and the RC:–RC decomposition technique. With the proposed configurations, the number of active elements is reduced to one or two, which is a significant reduction in comparision with the previously reported methods.

WOS: 000298836500016, …

In this paper, we study optimal in vitro realization of pulsatile coronary artery flows using newly proposed closed-loop feedback algorithms with a clearly defined mathematical performance objective, and we compare several flow control device technologies in terms of their ability to generate pulsatile flow signals as accurately as possible. In the literature, there are several published results for in vitro pulsatile flow realization systems. However, most of the proposed systems operate in an open-loop setting and use a single flow control device, and their performance is assessed mostly by graphical means without a clearly defined mathematical performance objective. Furthermore, some authors take the average of the generated pulsatile flow and compare it with the desired flow signal for performance analysis. What makes this work different from other published results in this area are: 1) the use of closed-loop feedback control rather than an open-loop approach; 2) the use of a clearly defined mathematical performance objective rather than a visual comparison of the generated and desired flow graphs; 3) newly proposed control algorithms with demonstrated performance improvements as compared to the published ones; 4) the use of multiple flow control devices, their performance comparisons, and optimal technology selection; and 5) not taking the average of the generated flow signal over several cycles for performance assessment, but instead using the nonaveraged actual flow signal and comparing it with the desired one. In pulsatile flow realization, what is important is the L1 distance between the desired and delayed versions of the generated flows in the steady state regime, and the defined mathematical performance objective is completely based on this point. Furthermore, there are 3 different flow control devices that are comparatively analyzed: the pneumatic valve, the servo valve, and an AC inverter driving a centrifugal pump. Finally, there are several new closed-loop control algorithms proposed in this paper: P-S , P-S predictive, P-S look ahead, and model-based nonlinear feed-forward, feed-forward predictive, and feed-forward look-ahead control. Each algorithm's performance is compared with that of PID performance as a benchmark test to demonstrate performance improvements. By proper selection of the flow control device, and optimal selection of the control algorithm and its parameters, we were able to achieve up to 75% reduction in error.

A simple, but general, synthesis method is given for the simulation of resistively terminated LC ladder circuits. The method is based on a new basic cell (BC) introduced in this work. The proposed method converts resistively terminated LC ladder circuits into inductorless active circuits involving only second-generation current conveyors (CCII±), grounded resistors and grounded capacitors. Hence it is suitable for fully integrated circuit design.

In this paper, a new floating analog memristance simulator circuit based on second generation current conveyors and passive elements is proposed. Theoretical derivations are presented which decribe the circuit characteristics. The hardware of proposed simulator circuit is built using commercially available components. Theoretical derivations are validated with PSPICE simulation and experimental results. Performance of circuit was tested with simple example circuits. All results show that proposed simulator circuit provides frequency dependent pinched hysteresis loop and nonvolatility features. Exciting frequency, minimum and maximum memristance values and memristance range can be adjustable with simple passive element values. Simulator circuit has a frequency range of 1[Formula: see text]Hz to 40[Formula: see text]kHz.

WOS: 000306287700007, A new circuit configuration for the realisation of an electronically tunable sinusoidal oscillator is presented. The proposed circuit uses only one current backward transconductance amplifier (CBTA), two grounded capacitors and one resistor. Using current controlled CBTA (CC-CBTA) instead of the CBTA, the resistor can be completely removed. It has also current-mode (CM) and voltage-mode (VM) outputs, simultaneously. The workability of the proposed structure has been demonstrated by both simulation and experimental results.

WOS: 000277662900002, In this paper, a new multi-terminal active component, namely current backward transconductance amplifier (CBTA) is proposed. The design procedure for the systematic realization of current-mode ladder filters using proposed active component is also presented. In order to demonstrate that the CBTA considerably simplifies the leapfrog structure of the current-mode ladder filters, a fifth-order Butterworth low-pass filter that requires a minimum of active components is presented. The theoretical results are demonstrated by using PSPICE simulation. (C) 2009 Elsevier GmbH. All rights reserved.

Patients, with renal failure, can be taken to the hemodialysis after fistula or graft surgery. In hemodialysis, blood is pumped with the help of the artificial kidney machine and the waste product from the blood is filtered and blood is returned to the patients after cleaning process. AV graft implantation is the creation of a polytetrafluoroethylene (PTFE) bridge a bridge between the arteries and veins. In this study simulation of the pulsatile flow signal in the AV graft and vein connection is aimed experimentally. Suitable for this purpose AC centrifugal pump, pump driver card, pneumatic valve, data acquisition card, flow meters and other equipments are used for close loop control mechanism in laboratory. Pulsatile waveforms obtained by AC centrifugal pump and pneumatic valve performance are compared to each other in close loop control. The results showed that AV graft signal can be modeled by AC centrifugal pump and pneumatic valve successfully. Current study could be a guide and motivation to the establishment of the different experimental systems in future.

WOS: 000266329400012, In this letter, a new floating inductance simulator circuit is presented. The proposed structure consists of only one grounded capacitor without any external resistors and two different active elements. The active elements are dual-output current-controlled current conveyor (DO-CCCII) and operational transconductance amplifier (OTA). The proposed inductance simulator can be tuned electronically by changing the biasing current of the DO-CCCIIs or by changing the current of the OTA. Moreover, the circuit does not require any conditions of component matching. It has a good sensitivity performance with respect to tracking errors. As an application, the proposed inductance simulator is used to construct a fourth-order resistively terminated LC band-pass filter. The theoretical analysis is verified by the SPICE simulation results. (C) 2008 Elsevier GmbH. All rights reserved.

WOS: 000262504400004, A new floating immittance function simulator circuit is proposed using two different active elements, a dual-output second generation current conveyor (DO-CCII) and an operational transconductance amplifier (OTA). The presented circuit can realize a positive and negative floating inductor, capacitor and resistor depending on the passive component selection. Since the passive elements are all grounded, this circuit is suitable for fully integrated circuit design. The circuit does not require any component matching conditions, and it has a good sensitivity performance with respect to tracking errors. Moreover, the proposed positive and negative inductance, capacitor and resistor simulator can be tuned electronically by changing the biasing current of the OTA or can be controlled through the grounded resistor or capacitor. The proposed floating inductor simulator circuit is demonstrated by using a SPICE simulation for 0.35 mu m TSMC CMOS technology. The proposed circuit consumes an average power of 1 mW using +/- 1.5 V supply voltages.

The authors propose two new configurations suitable for voltage-mode filter responses. It is possible to realise the most general nth-order and second-order voltage-mode transfer functions using these configurations. The first configuration uses a single current differencing buffered amplifier (CDBA) and RC:-RC decomposition technique to realise high order response. With this configuration the number of active elements is reduced to one compared to the previously reported method. The second configuration uses three CDBAs at most and state-space technique to realise second-order responses. The proposed filters seem to be versatile and suitable for the analogue signal processing. Independent parameters in the second configuration give flexibility to design. Proper choice of these parameters optimises the sensitivities.

A new filter circuit is proposed for the realisation of nth-order lowpass current-mode transfer function with unity gain by the active-RC circuit containing a minimum number of capacitors, n resistors and n+1 current conveyors. All of the current conveyors are either of the inverting or the noninverting type and they act as unity gain current followers. This makes the proposed circuit simple and attractive for current-mode operation.