165 results on '"Herdt, Vladimir"'
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2. Register-Transfer-Ebene Korrespondenzanalyse
3. Schlussfolgerung
4. Validierung von Firmware-basiertem Power Management mit virtuellen Prototypen
5. Präliminarien
6. Abdeckungsgesteuertes Testen für skalierbare Verifikation virtueller Prototypen
7. Formale Verifikation von SystemC-basierten Entwürfen durch symbolische Simulation
8. Verifizierung von eingebetteten Software-Binärdateien mit Hilfe virtueller Prototypen
9. Eine Open-Source RISC-V Evaluierungsplattform
10. SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification
11. Validation of Firmware-Based Power Management using Virtual Prototypes
12. Register-Transfer Level Correspondence Analysis
13. Coverage-Guided Testing for Scalable Virtual Prototype Verification
14. Verification of Embedded Software Binaries using Virtual Prototypes
15. Formal Verification of SystemC-Based Designs using Symbolic Simulation
16. An Open-Source RISC-V Evaluation Platform
17. Preliminaries
18. Introduction
19. The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research
20. SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware
21. Conclusion
22. Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform
23. SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification
24. Verbessertes virtuelles Prototyping
25. Extensible and Configurable RISC-V Based Virtual Prototype
26. Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling
27. RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms
28. RISC-V based virtual prototype: An extensible and configurable platform for the system-level
29. Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
30. Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges
31. Enhanced Virtual Prototyping
32. Validation of Firmware-Based Power Management using Virtual Prototypes
33. Coverage-Guided Testing for Scalable Virtual Prototype Verification
34. Preliminaries
35. Verification of Embedded Software Binaries using Virtual Prototypes
36. Register-Transfer Level Correspondence Analysis
37. Formal Verification of SystemC-Based Designs using Symbolic Simulation
38. Conclusion
39. An Open-Source RISC-V Evaluation Platform
40. Introduction
41. On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study
42. Dynamic Partial Order Reduction in Stateful Model Checking
43. Experiments
44. Heuristic Symbolic Subsumption
45. State Subsumption Reduction
46. Static Partial Order Reduction in Stateful Model Checking
47. Preliminaries
48. Introduction
49. Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction
50. Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification
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