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This work presents results of three distinct radiation tests performed upon a fault-tolerant data acquisition system comprising a design diversity redundancy technique. The first and second experiments are Total Ionizing Dose (TID) essays, comprising gamma and X-ray irradiations. The last experiment considers single event effects, in which two heavy ion irradiation campaigns are carried out. The case study system comprises three analog-to-digital converters and two software-based voters, besides additional software and hardware resources used for controlling, monitoring and memory management. The applied Diversity Triple Modular Redundancy (DTMR) technique, comprises different levels of diversity (temporal and architectural). The circuit was designed in a programmable System-on-Chip (PSoC), fabricated in a 130nm CMOS technology process. Results show that the technique may increase the lifetime of the system under TID if comparing with a non-redundant implementation. Considering the heavy ions experiments the system was proved effective to tolerate 100% of the observed errors originated in the converters, while errors in the processing unit present a higher criticality. Critical errors occurring in one of the voters were also observed. A second heavy-ion campaign was then carried out to investigate the voters reliability, comparing the dynamic cross-section of three different software-based voter schemes implemented in the considered PSoC.

This abstract presents an experimental study of the impact of using a high flux in radiation ground tests on the measured cross-section of SRAMs. Experimental results obtained with 15 MeV protons will show that using a high particle flux makes the measured cross-section increase by almost 1 order of magnitude.

This paper describes the main failure mechanism of charge redistribution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) under radiation. Results of two different radiation experiments (gamma and X-ray) each considering two identical 130nm, 8-bit SAR ADCs, operating with distinct sampling rates, showed that lower sampling frequencies cause the converters to fail at lower accumulated dose, while increasing the sampling frequency increases the converters robustness to radiation. A SPICE model of a SAR ADC is used to simulate radiation induced leakage effects, considering the same technology node and operating conditions of the tested converters. A very good agreement between simulation results and gamma irradiation experimental data allows us to explain the main failure mechanism, which is related to leakage in switches connected to the programmable capacitor array of the internal DAC of the converter.

We evaluate the sensitivity of neuromorphic inference accelerators based on silicon-oxide-nitride-oxide-silicon (SONOS) charge trap memory arrays to total ionizing dose (TID) effects. Data retention statistics were collected for 16 Mbit of 40-nm SONOS digital memory exposed to ionizing radiation from a Co-60 source, showing good retention of the bits up to the maximum dose of 500 krad(Si). Using this data, we formulate a rate-equation-based model for the TID response of trapped charge carriers in the ONO stack and predict the effect of TID on intermediate device states between “program” and “erase.” This model is then used to simulate arrays of low-power, analog SONOS devices that store 8-bit neural network weights and support in situ matrix–vector multiplication. We evaluate the accuracy of the irradiated SONOS-based inference accelerator on two image recognition tasks—CIFAR-10 and the challenging ImageNet data set—using state-of-the-art convolutional neural networks, such as ResNet-50. We find that across the data sets and neural networks evaluated, the accelerator tolerates a maximum TID between 10 and 100 krad(Si), with deeper networks being more susceptible to accuracy losses due to TID.

In this article, a commercial programmable system-on-chip (PSoC 5, from Cypress Semiconductor) is tested under heavy-ion irradiation with a focus on the analog-to-digital interface blocks of the system. For this purpose, a data acquisition system (DAS) was programmed into the device under test and protected with a design diversity redundancy technique. This technique implements different levels of diversity (architectural and temporal) by using two different architectures of converters (a $\Sigma \Delta $ converter and two successive approximation register (SAR) converters) operating with distinct sampling rates. The experiment was performed in a vacuum chamber, using a 16 O ion beam with 36-MeV energy and sufficient penetration into the silicon to produce an effective linear energy transfer (LET) of 5.5 MeV/mg/cm2 at the active region. The average flux was approximately 350 particles/s/cm2 for 246 min. The individual susceptibility of each converter to single-event effects is evaluated, as well as the whole system cross section. Results show that the proposed technique is effective to mitigate errors originating at the converters since 100% of such errors were corrected by using the diversity redundancy technique. Results also show that the processing unit of the system is susceptible to hangs that can be mitigated using watchdog techniques.

We investigate, through measurements and simulations, the possible direct ionization impact on the accelerator soft-error rate (SER), not considered in standard qualification approaches. Results show that, for a broad variety of state-of-the-art commercial components considered in the 65-16-nm technological range, indirect ionization is still expected to dominate the overall SER in the accelerator mixed-field. However, the derived critical charges of the most sensitive parts, corresponding to ~0.7 fC, are expected to be at the limit of rapid direct ionization dominance and soft-error increase., This work was supported in part by the European Union’s Horizon 2020 Research and Innovation Program under Grant 721624 and in part by the European Space Agency (ESA/ESTEC) at the University of Jyväskylä under Contract 4000124504/18/NL/KML/zk

In the aerospace industry, commercial-off-the-shelf (COTS) static random access memories (SRAMs) are a cost-effective solution for obtaining high performance at the system level, which is difficult to obtain using space-qualified components. In addition, the usage of dynamic voltage scaling (DVS) is commonly used in space environments, where low power consumption is a critical issue. This article presents an analysis of the sensitivity against single-event upsets (SEUs) of various COTS bulk SRAMs and advanced low-power SRAMs (A-LPSRAMs) against proton radiation when using DVS to save power. Experimental results will show clear evidence that the sensitivity to SEUs increases when the power is lowered. Two sets of successive technologies (130-, 90-, and 65-nm bulk SRAMs, and 150- and 110-nm A-LPSRAMs) are evaluated against 15-MeV protons and compared with results of 14-MeV neutrons presented in a previous work. Experimental data are finally compared with analytical simulations obtained by using the multiscales single-event phenomena predictive platform (MUSCA-SEP3) Monte Carlo tool to predict the effect of DVS on the SEE sensitivity on more modern technologies in the ITRS/IRDS roadmap.

International audience; The field of radiation effects in electronics research includes unknowns for every new device, node size, and technical development. In this study, static and dynamic test methods were used to define the response of a self-refresh DRAM under neutron irradiation. The neutron-induced effects were investigated and characterised by event cross sections, soft-error rate, and bitmaps evaluations, leading to an identification of permanent and temporary stuck cells, single-bit upsets, and block errors. Block errors were identified in different patterns with dependency in the addressing order, leading to up to two thousand faulty words per event, representing a real threat from a user perspective, especially in critical applications. An analysis of the damaged cells’ retention time was performed, showing a difference in the efficiency of the self-refresh mechanism and a read operation. Also, a correlation of the fault mechanism that generates both single-bit upsets and stuck bits is proposed. Post- irradiation high-temperature annealing procedures were applied, showing a recovery behaviour on the damaged cells.

International audience; The R2E project at CERN has tested a few commercial SRAMs and a custom-designed SRAM, whose data are complementary to various scientific publications. The experimental data include low- and high-energy protons, heavy ions, thermal, intermediate- and high-energy neutrons, high-energy electrons and high-energy pions.

International audience; Approximate Computing (AxC) is a well-known paradigm able to reduce the computational and power overheads of a multitude of applications, at the cost of a decreased accuracy. Convolutional Neural Networks (CNNs) have proven to be particularly suited for AxC because of their inherent resilience to errors. However, the implementation of AxC techniques may affect the intrinsic resilience of the application to errors induced by Single Events in a harsh environment. This work introduces an experimental study of the impact of neutron irradiation on approximate computing techniques applied on the data representation of a CNN.

This article presents an experimental study on the sensitivity of a commercial-off-the-shelf (COTS) bulk 65-nm static random access memory (SRAM) under 15.6 MeV proton irradiation when powered up at ultralow bias voltage. Tests were run on standby and while reading the memory. Results show obvious evidence indicating that decreasing the bias voltage below 1 V exponentially increases the number of observed errors. Single-bit upsets (SBUs) and multiple-cell upsets (MCUs) (mostly with vertical shapes according to the manufacturers' layout) are reported and their behavior is analyzed in this article. Predictions on the single-event upset (SEU) sensitivity obtained with the multiscales single-event phenomena predictive platform (MUSCA-SEP3) modeling tool are also provided and compared with the experimental results. These are also compared with 14.2 MeV neutrons, showing a significant difference in the cross sections for both irradiation sources. Total ionizing dose (TID) tests and GEANT4 simulations were also run to check for the reason behind the difference in the cross section between these two particles., This work was supported in part by the Spanish MINECO project TIN2017-87237. The work at the CNA has been supported in part by the Spanish Ministry of Economy and Competitiveness under project ESP2015-68245-C4-4-P.

International audience; In harsh radiation environments, it is well known that the angle of incidence of impinging particles against the surface of the operating devices has significant effects on their sensitivity. This article discusses the sensitivity underestimations that are made if particle isotropy is not taken into account, by means of an analytical study made with a single-event upset predictive platform. To achieve this goal, experimental results carried out with a commercial-off-the-shelf (COTS) bulk 130-nm nonvolatile static random access memory (SRAM) for various incident angles on 14.2 MeV neutrons are first discussed. Then, a modeling tool called multiscales single-event phenomena predictive platform (MUSCA-SEP3) is used to predict the sensitivity of this memory under the same environmental conditions. Predictions and experimental results will be cross-checked, and therefore, the feasibility of this tool will be demonstrated for testing any other incident angle. Finally, an isotropic environment and an XY SRAM array will be emulated with MUSCA in order to demonstrate that the asymmetrical cross sections that were observed experimentally for various incidence angles are due to the underlying asymmetry of the metalization/passivation layers within the device with respect to its active silicon. Conclusions will finally be drawn as for the importance of taking into account particle isotropy in radiation-ground tests.

International audience; This paper identifies the failure modes of a commercial 130-nm ferroelectric random access memory. The devices were irradiated with heavy-ion and pulsed focused X-ray beams. Various failure modes are observed, which generate characteristic error patterns, affecting isolated bits, words, groups of pages, and sometimes entire regions of the memory array. The underlying mechanisms are discussed.

International audience; The impact of heavy-ions on commercial Ferroelectric Memories (FRAMs) is analyzed. The influence of dynamic and static test modes as well as several stimuli on the error rate of this memory is investigated. Static test results show that the memory is prone to temporary effects occurring in the peripheral circuitry, with a possible effect due to fluence. Dynamic tests results show a high sensitivity of this memory to switching activity of this peripheral circuitry.

16nm single-level-cell (SLC) NAND flash memories with 1-bit ECC are shown to have excellent robustness to soft errors induced by terrestrial neutron radiation and alpha particles. Accelerated stress test studies were done at TRIUMF Neutron Facility for neutron induced soft errors and using calibrated alpha sources for accelerated alpha particle testing. Our results demonstrate excellent robustness of the memory device to soft error latch-up and single event upsets. Additionally, we report cross-site correlation results of accelerated alpha particle testing of 16nm NAND flash memories by comparing test results using Am-241 and Th-232 foils for higher confidence in the failure rate calculations. An acceleration factor of 1.66 × 104 between the two foils was used.

This paper presents a single event upset (SEU) sensitivity characterization at ultralow bias voltage of three generations of commercial off-the-shelf static random access memories (SRAMs) manufactured in 130-, 90-, and 65-nm CMOS processes. For this purpose, radiation tests with 14.2-MeV neutrons were performed for SRAM power supplies ranging from 0.5 to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool multiscales single event phenomena predictive platform. Large-scale single event latchups and single event functional interrupts (SEFIs), observed in the 90- and 130-nm SRAMs, respectively, are also presented and discussed. Fil: Clemente, Juan Antonio. Universidad Complutense de Madrid; España Fil: Hubert, Guillaume. Office National d'Etudes et de Recherches Aérospatiales; Francia Fil: Fraire, Juan Andres. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba; Argentina. Université Grenoble-Alpes; Francia. Universidad Nacional de Córdoba; Argentina Fil: Franco, Francisco J.. Universidad Complutense de Madrid; España Fil: Villa, Francesca. Université Grenoble-Alpes; Francia Fil: Rey, Solenne. Université Grenoble-Alpes; Francia Fil: Baylac, Maud. Université Grenoble-Alpes; Francia Fil: Puchner, Helmut. Cypress Semiconductor Corporation; Estados Unidos Fil: Mecha, Hortensia. Universidad Complutense de Madrid; España Fil: Velazco, Raoul. Universidad Nacional de Córdoba; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Córdoba; Argentina. Université Grenoble-Alpes; Francia

This conference presents the recipients of the Outstanding Conference Paper Award from the 2015 IEEE Nuclear and Space Radiation Effects Conference.

Low- and high-energy proton experimental data and error rate predictions are presented for many bulk Si and SOI circuits from the 20-90 nm technology nodes to quantify how much low-energy protons (LEPs) can contribute to the total on-orbit single-event upset (SEU) rate. Every effort was made to predict LEP error rates that are conservatively high; even secondary protons generated in the spacecraft shielding have been included in the analysis. Across all the environments and circuits investigated, and when operating within 10% of the nominal operating voltage, LEPs were found to increase the total SEU rate to up to 4.3 times as high as it would have been in the absence of LEPs. Therefore, the best approach to account for LEP effects may be to calculate the total error rate from high-energy protons and heavy ions, and then multiply it by a safety margin of 5. If that error rate can be tolerated then our findings suggest that it is justified to waive LEP tests in certain situations. Trends were observed in the LEP angular responses of the circuits tested. As a result, grazing angles were the worst case for the SOI circuits, whereas the worst-case angle was at or nearmore » normal incidence for the bulk circuits.« less

In 2009 Tausch developed a simple equation to predict the cumulative probability of a single uncorrectable (double bit) error occurring within Hamming protected memory as the number of random upsets increase. This paper furthers that work by: 1) developing a simplified equation that predicts the number of failing addresses vs. random upsets in Hamming protected memories, 2) showing the range over which this simplified equation matches more complicated, 3) proving the validity of this equation through radiation testing, 4) showing how this equation can be used to improve test techniques in various simulator environments and 5) showing how this equation can be used to better analyze test results and to understand and predict the behavior of Hamming memories in radiation environments. An approach will be described to better calculate upset cross-sections of Hamming protected SRAMs in heavy ion environments.

International audience; This paper presents heavy-ion and proton radiation test results of a 90 nm COTS SRAM with stacked structure. Radiation tests were made using high penetration heavy-ion cocktails at the HIF (Belgium) and at RADEF (Finland) as well as low energy protons at RADEF. The heavy-ion SEU cross-section showed an unusual profile with a peak at the lowest LET (heavy-ion with the highest penetration range). The discrepancy is due to the fact that the SRAM is constituted of two vertically stacked dice. The impact of proton testing on the response of both stacked dice is presented. The results are discussed and the SEU cross-sections of the upper and lower layers are compared. The impact of the stacked structure on the proton SEE rate is investigated.

This paper presents the characterization of the sensitivity to 14-MeV neutrons of a Commercial Off-The-Shelf (COTS) 90-nm Static Random Access Memories (SRAMs) manufactured by Cypress Semiconductor, when biased at ultra low voltage. Firstly, experiments exposing this memory at 14-MeV neutrons, when powering it up at bias voltages ranging from 0.5V to 3.3V, are presented and discussed. These results are in good concordance with theoretical predictions issued by the modeling tool MUSCA-SEP 3 (MUlti-SCAles Single Event Phenomena Predictive Platform). Then, this tool has been used to obtain Soft Error Rate (SER) predictions at different altitudes above the Earth’s surface of this device vs. its bias voltage. Finally, the effect of contamination by α articles has also been estimated at said range of bias Voltages.

International audience; This paper addresses a well-known problem that occurs when memories are exposed to radiation: the determination if a bit flip is isolated or if it belongs to a multiple event. As it is unusual to know the physical layout of the memory, this paper proposes to evaluate the statistical properties of the sets of corrupted addresses and to compare the results with a mathematical prediction model where all of the events are single bit upsets. A set of rules easy to implement in common programming languages can be iteratively applied if anomalies are observed, thus yielding a classification of errors quite closer to reality (more than 80% accuracy in our experiments).

In this paper, the impact of total ionizing dose on the data retention behavior of a silicon-oxide-nitride-oxide-silicon-based NOR flash nonvolatile memory is studied for the first time on a deep sub-micron 65-nm complementary metal-oxide semiconductor technology node. The fundamental nonvolatile single-level cell memory element utilizes uniform Fowler-Nordheim (F-N) tunneling for both program and erase operations. The data retention behavior is investigated on a 4-Mb NOR Flash-based memory array at space-level total ionizing dose (TID) exposures up to 500 krad. Excessive TID exposure reduces the program-erase window but improves the thermal emission coefficient and, hence, improves data retention.

While single bit upsets on memories and storage elements are mitigated with either the use of redundancy and/or error correction codes, Multiple-Cell-Upsets (MCU) may become a significant threat to the integrity of systems when the corrupted cells belong to the same word. In this paper, we identify four types of MCUs as they were recorded during several irradiations under an atmospheric-like neutron beam (ISIS facility). An analysis is done on the underlying reasons of occurrence of each MCU type, as well as their shapes and sizes in order to classify them. The results of this work concern a commercial 90 nm SRAM that was tested under an atmospheric neutron beam in static and dynamic mode. It is shown that, when the memory is in dynamic mode, not only the typical MCUs that involve a few flipped cells may appear but also large clusters of upsets are possible to occur with hundreds or even thousands of cells being affected.

International audience; In previous works, we have demonstrated the importance of dynamic mode testing of SRAM components under ionizing radiation. Several types of failures are difficult to expose when the device is tested under static (retention) mode. With the purpose of exploring and defining the most complete testing procedures and reveal the potential hazardous behaviors of SRAM devices, we present novel methods for the dynamic mode radiation testing of SRAMs. The proposed methods are based on different word address accessing schemes and data background: Fast Row, Fast Column, Pseudorandom, Adjacent (Gray) and Inverse Adjacent (Gray). These methods are evaluated by heavy ion and atmospheric-like neutron irradiation of two COTS SRAMs of 90 nm and 65 nm technology.

International audience; Statistical properties of experiments in SRAMs with only SBUs are mathematically evaluated. Strategies using deviations of actual data from theory are proposed to extract MCUs from the bulk of errors regardless the SRAM internal structure.

International audience; Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.

International audience; Methodologies are proposed for in-depth statistical analysis of Single Event Upset data. The motivation for using these methodologies is to obtain precise information on the intrinsic defects and weaknesses of the tested devices, and to gain insight on their failure mechanisms, at no additional cost. The case study is a 65 nm SRAM irradiated with neutrons, protons and heavy ions. This publication is an extended version of a previous study.

Established methods for testing ESD robustness of high-voltage pins in smart power CMOS can lead to erroneous results. This paper investigates both LDNMOS and certain types of SCRLDMOS (SCRs embedded in LDNMOS) high-voltage clamps for safe-operating-area collapse due to trigger voltage (V t1) walk-in after transmission-line pulsing (TLP) corresponding to leakage-current increase below I t2. For the first time, the evolution of V t1 as a function of the number of TLP pulses and their magnitude is shown. Furthermore, some high-voltage clamps that are robust on their own are shown to walk-in in certain circuit environments that present high capacitance. The physical mechanism for this leakage enhancement and trigger-voltage walk-in has been established through failure analysis to be consistent with melt filament growth perhaps aided by metal migration. A simple phenomenological model is proposed to explain this behavior. Finally, the ability to avoid such V t1 collapse in SCRLDMOS through simple layout changes is shown.

Final passivation planarization is achieved by optimizing the stack height and trench width for technologies that are sensitive to passivation planarization like image sensor processes. Deposition profiles obtained by using our topography simulator elsa (Enhanced Level Set Applications) predict a range of trench width, stack height, and the thickness of the deposited layers which lead to a sufficient planarization margin. Furthermore, these predictions enable design of trenches with a sufficient side wall and bottom coverage in order to guarantee a proper moisture seal.

A methodology is proposed for the statistical analysis of memory radiation test data, with the aim of identifying trends in the single-even upset (SEU) distribution. The treated case study is a 65nm SRAM irradiated with neutrons, protons and heavy-ions.

Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.

International audience; Various failure scenarios may occur during irradiation testing of SRAMs, which may generate different characteristic Multiple Cell Upset (MCU) error patterns. This work proposes a method based on spatial and temporal criteria to identify them.

The impact of heavy-ions on commercial Ferroelectric Memories (FRAMs) is analyzed. The influence of different test modes (static and dynamic) on this memory is investigated. Static test results show that the memory is prone to temporary effects occurring in the peripheral circuitry. Dynamic tests results show a high sensitivity of this memory to heavy-ions.

Multi-bit upset (MBU) events collected from accelerated soft error rate (SER) measurements performed with a quasi-monoenergetic neutron beam were analyzed with a threefold purpose. The first goal was to qualitatively assess the applicability and effectiveness of single-bit Error Detection And Correction algorithms and circuits (EDAC). The second goal was to investigate the relationship with the memory core P-well tapping scheme. And the third goal was to identify "preferred" MBU shapes. The results showed that the memory architecture is critical in affecting the single-bit EDAC effectiveness. Also, it was put in evidence that the tapping scheme is very effective in reducing the MBU rate. And finally it was noted that the predominant MBU shape is strongly influenced by the vertical and horizontal distance of the active nodes of the memory cells.

A triple-well scheme has been implemented on an 18-Mb fast synchronous SRAM by using a high energy implant to evaluate its impact on the alpha-particle-induced accelerated soft error rate (ASER). The device uses a single poly 0.15-/spl mu/m CMOS process. The SER FIT rates have been measured from silicon with and without the triple well. In contrast to the historical literature, the measured FIT rate of the triple-well silicon shows a significant degradation of the SER FIT rate. Detailed analysis of bitmap for the flipped cell was employed to identify the degradation mechanism. It is found that the increase of the p-well resistivity and the effective contact to the p-well is the main reason of the degradation. However, in the region of solid tap to both n-well and p-well, the FIT rate is close but slightly higher than the control wafers. In addition, a trade-off between the NMOS and PMOS region is identified using two-dimensional numerical analysis. The results prove that an optimization of the well connections are needed for the triple-well scheme and the SER improvement relies on the optimization of the tradeoff effect. For high energy particles, which can penetrate much deeper into the silicon substrate, the triple well is expected to be helpful to limit the charge collection.

One of the challenges that technology computer-aided design must meet currently is the analysis of the performance of groups of components, interconnects, and, generally speaking, large parts of the IC. This enables predictions that the simulation of single components cannot achieve. In this paper, we focus on the simulation of backend processes, interconnect capacitances, and time delays. The simulation flows start from the blank wafer surface and result in device information for the circuit designer usable from within SPICE. In order to join topography and backend simulations, deposition, etching, and chemical mechanical planarization processes in the various metal lines are used to build up the backend stack, starting from the flat wafer surface. Depending on metal combination, line-to-line space, and line width, thousands of simulations are required whose results are stored in a database. Finally, we present simulation results for the backend of a 100-nm process, where the influence of void formation between metal lines profoundly impacts the performance of the whole interconnect stack, consisting of aluminum metal lines, and titanium nitride local interconnects. Scanning electron microscope images of test structures are compared to topography simulations, and very good agreement is found. Moreover, charge-based capacitance measurements were carried out to validate the capacitance extraction, and it was found that the error is smaller than four percent. These simulations assist the consistent fabrication of voids, which is economically advantageous compared to low-/spl kappa/ materials, which suffer from integration problems.

International audience; We present novel methods for the dynamic mode radiation testing of SRAMs, based on different address accessing schemes: Fast Row, Fast Column and Pseudorandom. These methods are evaluated by heavy ion irradiation of two SRAMs.