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This paper presents an RF-DC converter integrated circuit (IC) with ~307- $\mu \text{W}$ output power capable of powering individual health monitoring systems. The IC is designed with an on-chip adaptive impedance matching network to accommodate a wide input RF power variation and extend the operating frequency range. The system is composed of an antenna, an adaptive impedance matching network, a three-stage full-wave RF-DC rectifier, and a low-power digital control loop. A 5-bit successive-approximation-register analog-to-digital converter (ADC) is employed to monitor the dc output voltage and tune a 4-bit binary-weighted capacitor array in the matching network through the control loop. The complete system is designed and fabricated in standard 0.13- $\mu \text{m}$ CMOS technology. The post-simulated power consumption of the 5-bit ADC and digital control loop is 208 and 87 nW, respectively. Measurement results show that the impedance tuning mechanism can extend the optimal frequency range where the efficiency is higher than 80% of its peak value from 150 MHz (800–950 MHz) for the case without tuning to 220 MHz (780 MHz–1 GHz) when the impedance is adjusted using the control loop. The system achieves a measured end-to-end peak efficiency of 29.3% and is able to deliver an output power higher than 300 $\mu \text{W}$ with an output voltage and current of 1.75 V and 175.4 $\mu \text{A}$ , respectively. The active chip area is 0.17 mm2 including the control loop and ADC. [ABSTRACT FROM AUTHOR]

Thisbrief studies the effect of nonideal decoupling structureson the performanceof single-endedcircuits operating at the millimeter wave frequency range. Based on a first-order approximation, an upper limit on the impedance of decoupling structures is derived, given a prespeci- fied accepted degradation in insertion loss. To verify the analysis, a 110-GHz single-ended amplifier with a compact decoupling structure based on distributed interdigitized metal-oxide-metal capacitor is implemented. The full-wave electromagnetic simulations of the decoupling structure show an input impedance of (0.47 - j0.12) Ω at 110 GHz, and the magnitude is less than 1 Ω from 82 to 144 GHz. The degradation in the insertion loss of the matching network is simulated to be less than 0.5-dB compared with the use of ideal decoupling capacitors at 110 GHz. The area of the decoupling structure is 18x100 µm² when implemented in 65-nm digital CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a visible light communication (VLC) system for indoor applications. The system employs a high-sensitivity integrated circuit (IC) receiver with detection levels in the microwatts range. The proposed link is a lighting compatible VLC system enabled by the low noise floor of the IC receiver and capable of establishing a VLC link in the gigabit-per-second range with only 250 lux illuminance or 600-μW transmitted optical power from a high-speed 680-nm laser diode source. Dedicated optics is used for light steering and for focusing the transmitted power toward the receiver to maximize the collected optical power. The receiver is implemented in AMS 0.35 μm CMOS technology with integrated photodiodes. An error-free VLC link with a bit error rate (BER) <10−9 is measured up to 1.8 Gb/s and a VLC-compliant BER below 10−3 is measured up to 2.5 Gb/s with on–off-keying modulation over 12 m link distance. To our knowledge, this is the first reported IC receiver-based VLC link in the Gb/s range. [ABSTRACT FROM PUBLISHER]

This work presents an inductorless, 10 Gbps automatic gain control (AGC) circuit including a speed enhanced variable gain amplifier (VGA), a power detector, a comparator, and a novel exponential function generator for extended dB-linear performance. Third-order interleaved feedback technique is utilized in the current steering VGA stage to achieve 10 Gb/s operation without using on-chip inductors. A stagger-tuned switching architecture for CMOS exponential function generation is proposed to achieve a dB-linear gain control range of \sim40\;\textdB with better than \pm 1\;\textdB gain error. The relationship between tuning range and approximation error is analyzed and a novel current ratio generator circuit is proposed to implement the approximation functions in the current domain. The AGC circuit achieves a highest data rate of 10 Gb/s for 2^31-1 PRBS input, maintaining 360\;\textmV_\textp-p constant differential output with a BER <10^-12 for an input dynamic range of \sim24\;\textdB (15–240 \textmV_\textp-p). Fabricated in IBM 0.13 \upmu \textm CMOS technology, the chip draws 50 mW from a 1.2 V power supply (excluding the output buffer) and occupies an active area of 0.4\;\textmm^2. [ABSTRACT FROM PUBLISHER]

Mechanical to electrical energy conversion employing variable capacitors is assisted by electronic circuits that can have synchronous or asynchronous architectures. The later does not require synchronization of electrical events with mechanical motion, which eliminates difficulties in gate clocking and the power consumption associated with intelligent control circuitry. However, implementation of asynchronous energy harvesting circuits with the mechanical-to-electrical converter can be detrimental to the performance of the converter when done without concurrent optimization of the mechanical device and the circuit, an aspect mainly overlooked in the literature. This paper carries out system level analysis of electrostatic micro-generators with asynchronous control and charge fly-back mechanism to optimize the useful energy generated by the harvester. Our theoretical and experimental investigations show that there is an optimum value for either the storage capacitor or cycle number for maximum scavenging of ambient energy via asynchronous electrostatic transduction. The analysis also indicates that the maximum power is extracted from the system when approaching synchronization of mechanical and electrical events. However, there is a region of interest where the storage capacitor can be optimized to produce almost 70% of the ideal power, taken as the power harvested with synchronous converters when neglecting the power consumption associated with synchronizing control circuitry. Theoretical predictions are confirmed by measurements on an asynchronous energy harvesting circuit implemented with a macro-scale electrostatic converter prototype. [ABSTRACT FROM AUTHOR]

This paper proposes the use of N-push operation for combining the functions of the VCO and divider in the mm-wave frequency range. If employed in a PLL, the combined VCO/divider (C-VCO/D) would potentially provide wider tuning range than traditional mm-wave PLLs employing injection locked frequency dividers, thus exploiting the full range available in the 60 GHz band (57 GHz-64 GHz). The behavior of triple push oscillators based on injection locking theory is analyzed to study their various oscillation modes, their stability and the effect of mismatch on the oscillator performance. Design guidelines are provided for boosting the third harmonic power at a given power budget. Using 130 nm IBM CMOS technology, multiple versions of the triple push oscillator are implemented and characterized. A 55 GHz-65 GHz tuning range is obtained using a 206 pH tank inductance and requires Icore= 20 mA, and Ibuffer = 15 mA from a 1.4 V supply. For a tank inductance of 140 pH, a 63.2 GHz-72.4 GHz tuning range is obtained using Icore = 17 mA, and Ibuffer = 18 mA with a phase noise of -91 dBc/Hz at 10 MHz from the 63.2 GHz carrier and -95 dBc/Hz at 10 MHz from the 72.4 GHz carrier. [ABSTRACT FROM AUTHOR]

This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 μm CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of -116 dBc/Hz at 1 MHz offset from a 2.55 GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of -122.8 dBc/Hz at 1 MHz offset from a 4.77 GHz carrier. [ABSTRACT FROM AUTHOR]