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As to unreliable networks, like Ethernet, waiting for connection establishment can be inefficient during RDMA (Remote Direct Memory Access) transmission. Aiming at solving long waiting problem, a hardware supported RDMA method, DRDMA (Dynamic RDMA), was proposed in this paper. DRDMA, providing a new indirect transmission mode and corresponding dynamic switch policy based on traditional RDMA method, allowed starting RDMA transmission at the same time with connection establishment by sending packages first to indirect buffer in RNIC and copying them later to host memory, which was totally transparent to upper layers. Based on Gigabit Ethernet, we built node models of DRDMA method and set up simulation platforms to perform experiments. Experimental results show that for unreliable networks, DRDMA not only can solve the long waiting problem of connection establishment with little extra hardware cost, but also can provide higher transmission performance compared with traditional RDMA method.

Due to its high bandwidth, good maintainability and flexibility, Gigabit Ethernet is confoundedly suitable for high-performance server applications. As an interface between network and host, Ethernet controller has been continually evolving to meet the ever increasing communication demands being placed on it by enterprise applications. For the Ethernet, network links and physical devices, such as controller and switch, are likely to be out of order, which may result in system paralysis, service interruption and even intolerable consequence, especially when there are critical programs running on servers. In this scenario, Ethernet controller needs to not only achieve data reception and transmission, but also provide supports to the latest associate technology and standards. The objective of this paper therefore to design and implement an enhanced Gigabit Ethernet controller, called LCE5718, that provides fault tolerant transmission and prevention mechanism based on IEEE 802.3ad link aggregation and Network Controller Sideband Interface (NC-SI) respectively. Equipped with dual-port, LCE5718 is able to support link aggregation technology that can prevent connectivity loss even if one of the channels is out-of-order. In addition, we achieve a fault prevention mechanism in LCE5718 based on NC-SI. When prevention mechanism is adopted, potential device faults can be prevented by instantly reporting device's abnormal status to administrator and the corrective actions could be taken immediately. We also implemented LCE5718 in FPGA and performed experiments to evaluate its performance. The experiment results indicate that LCE5718 not only can guarantee fault tolerance transmission, but also can provide an effective prevention of network paralysis caused by device fault.

When multiple virtual machines (VMs) are running on the same physical device, inner-VM switching and VM's bandwidth allocation are usually achieved by hypervisor, without any NIC support. Although there have been several optimization algorithms for hypervisor, these software-based methods still can't be optimal solutions because of extra CPU workloads. Motivated by the studies, we proposed a VM-friendly NIC architecture that achieves inner-VM switching and bandwidth allocation functions based on hardware. In order to switch packets between VMs, the new architecture allows TX engine to forward packets from one TX queue to target VM's RX queue by providing an access of RX BD (Buffer Descriptor) ring to TX engine. On the other hand, we proposed a method to allocate each VM's bandwidth based on the RX statistics, significantly without any CPU cost. Experimental results demonstrate that the new NIC architecture not only reduces the CPU utilization for both inner-VM switching and bandwidth allocation, but also improve target VM's throughput for multiple VM, while maintain good compatibility with hypervisor.