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In this paper, a low-power accuracy-configurable block-based Carry Look-ahead Adder (AC-CLA) is proposed. The structure employs the voltage over scaling and number of approximate blocks as the approximation knobs for improving the energy consumption as well as the reliability and lifetime of the adder. While the former may be set in the design time as well as the runtime, the latter may only be invoked in the design time. In this adder, for a given accuracy level, some of the blocks work in the approximate mode by using over-scaled voltages. The block-based structure enables applying the overscaled voltage for each block independently. The efficacy of the adder depends on the number of the approximate blocks as well as the VOS voltage levels used for these blocks. The use of lower VOS voltage levels for the blocks responsible for lower significant bits which have higher switching activities is the key for reducing the power consumption of the adder while having the error within a tolerable limit. The structure requires few level shifters making the realization overhead low. The efficiency of the AC-CLA structure is studied using a 15 nm FinFET technology. The results of the study indicate that in the approximate mode up to 57% energy saving may be achieved. In addition, for this adder, the BTI induced delay degradation of the adder over 10 years decreases by up to 7% compared to 50% in the case of the exact operating mode. Finally, the efficacy of AC-CLA adder is assessed in a neural network for the classification application.

An energy–quality scalable coarse grain reconfigurable architecture (CGRA) based on the voltage overscaling (VOS) technique is presented. The approximation level of each processing element (PE) in the CGRA is determined by the applied VOS-determined voltage level. By employing the technique, the architecture may be configured for accurate or approximate modes of computation depending on a user-specified output quality-of-service target for a given application. More precisely, operating voltages used for performing various operations in the application dataflow graph are minimized subject to the output quality constraint by using an energy–quality tradeoff algorithm. To make the hardware implementation of the scheme more efficient, PEs are clustered into groups of (e.g., $3\times 1$ and $2\times 1$ ) voltage islands. To assess the efficacy of the proposed method in improving the power (energy) consumption and reliability of CGRAs, different combinations of minimum output quality constraints, voltage levels, and cluster sizes for several benchmarks are studied. Simulation results indicate considerable reductions in energy consumption (up to 43%) and aging rate (up to 73%) when compared with the conventional CGRA with perfect output quality (i.e., with no approximate computations).

Aims: Cholera is an acute diarrheal disease that can lead to severe dehydration and death. Antibiotic resistance is a big challenge in infective disease like Cholera. The present study aimed to understand the characteristics and trends of antibiotic resistance of V. cholerae isolations in and around Kashan, Iran. Instrument & Methods: In this descriptive cross-sectional study, samples were gathered using census method from 1998 to 2013 in Kashan, Iran. 1132 fecal samples of patients with acute diarrhea and 237 samples of suspected water samples were taken. The serotypes and biotypes were determined by an enzymatic method. Antibiotic susceptibility test was performed by using Disk Diffusion Method. Data were analyzed using SPSS 23 software. Fisher-exact and Chi-square tests were used to compare the statistical parameters. Findings: 96 fecal samples (8.5) and 18 water samples (7.6) were positive for Vibrio cholerae. Non-agglutinating (Nag) isolates (75.4) were more common than serotype Inaba (13.2) and Ogawa (11.4). Nag serotypes were mostly resistant to cefixime (44) and ampicillin (33). In contaminated water samples also the most frequent cases were Nag serotype (50). Nag serotype showed 22.2 of resistance to ampicillin and nitrofurantoin. Conclusion: Vibrio cholerae isolates in Kashan, Iran, are highly resistant to antibiotics, especially Nag serotypes.

This study was carried out to determine the effects of magnesium and vitamin E co-supplementation on wound healing and metabolic status in patients with diabetic foot ulcer (DFU). The current randomized, double-blind, placebo-controlled trial was conducted among 57 patients with grade 3 DFU. Participants were randomly divided into two groups to take either 250 mg magnesium oxide plus 400 IU vitamin E (n = 29) or placebo per day (n = 28) for 12 weeks. Compared with the placebo, taking magnesium plus vitamin E supplements reduced ulcer length (β [difference in the mean of outcomes measures between treatment groups] -0.56 cm; 95% CI, -0.92, -0.20; p = 0.003), width (β -0.35 cm; 95% CI, -0.64, -0.05; p = 0.02) and depth (β -0.18 cm; 95% CI, -0.33, -0.02; p = 0.02). In addition, co-supplementation led to a significant reduction in fasting plasma glucose (β -13.41 mg/dL; 95% CI, -20.96, -5.86; p = 0.001), insulin (β -1.45 μIU/ml; 95% CI, -2.37, -0.52; p = 0.003), insulin resistance (β -0.60; 95% CI, -0.99, -0.20; p = 0.003) and HbA1c (β -0.32%; 95% CI, -0.48, -0.16; p

In this work, the application of a voltage over-scaling (VOS) technique for improving the lifetime and reliability of coarse-grained reconfigurable architectures (GCRAs) is presented. The proposed technique, which may be applied to CGRAs used as accelerators for low-power, error-tolerant applications, reduces the (strongly voltage-dependent) wearout effects and the energy consumption of processing elements (PEs) whenever the error impact on the output quality degradation can be tolerated. This provides us with the ability to lessen the wearout and reduce energy consumption of PEs when accuracy requirement for the results is rather low. Multiple degrees of computational accuracy can be achieved by using different overscaled voltage levels for the PEs. The efficacy of the proposed technique is studied by considering the bias temperature instability. The study is performed for two error-resilient applications. The CGRAs are implemented with 15nm FinFET operating at a nominal supply voltage of 0.8V. In addition, supply voltages of 0.75, 0.7, 0.65, and 0.6V are considered as overscaled voltage levels for this technology. Based on the quality constraint requirements of the benchmarks, optimum overscaled voltage levels for various PEs are determined and utilized. The approach may provide considerable lifetime and energy consumption improvements over those of the conventional exact and approximate computation approaches.

This paper proposes a robust and energy-efficient hybrid TFET-FinFET 6T SRAM cell which takes advantage of the higher ON/OFF current ratio of TFETs compared to that of FinFETs to reliably hold and access data at ultra-low supply voltages. More precisely, in the proposed hybrid cell, to achieve low static currents along with high noise margins, TFETs are used for cross-coupled inverters, and to speed up the access time, high-performance FinFETs are utilized for access transistors. The paper also presents a dual-V t 6T SRAM, in which low-power (high-V t ) and high-performance (low-V t ) FinFETs are used for cross-coupled inverters and access transistors, respectively. For both SRAM cells, the V dd boost read-assist technique is employed to improve the read stability. Characteristics of both SRAMs are analyzed using HSPICE simulations for technologies with the gate length of 20 nm for a 128\times 128 SRAM array. Simulation results reveal that the lowest operating V dd for the dual-V t cell is 225 mV, whereas that of the hybrid cell is 125 mV. Moreover, to further decrease the access delay of the hybrid cell for 125 mV ≤ V dd ≤ 225 mV, negative Gnd read-assist technique and a boosted voltage for the row decoder are used. Finally, the paper presents a 125mV 2ns-access-time 16Kb SRAM array based on the proposed hybrid TFET-FinFET SRAM cell.

In this work, we investigate the co-dependency of die temperature and bias temperature instability (BTI) and their combined effect on the lifetime of VLSI circuits. The investigation considers the impact of die temperature in increasing the effect of the BTI as well as changes in the die temperature due to the BTI-induced threshold voltage alterations. In addition, the impact of workloads on the degree of the BTI-induced degradation in VLSI circuits is studied. This impact accounts for the direct influence of the signal probability of the internal nodes under the given workload as well as its indirect influence due to power consumption and temperature changes of the circuits. The study is performed by using a simulation framework that captures dynamic changes in the operating temperature and application workload. Simultaneous consideration of the dynamic workload and operating temperature enables one to accurately predict the circuit lifetime. To assess the accuracy of the proposed approach, the estimated delay degradations caused by the Negative BTI (NBTI) for some large circuits from ISCAS'89 and ITC'99 benchmark suites when circuits are simulated under dynamic (both temperature and workload are updated periodically), semi-static (either temperature or workload is updated periodically), and static (no updating is performed) scenarios are compared. Simulation results obtained in a 45 nm CMOS technology, reveal that the predicted timing degradation in the case of the dynamic scenario is significantly different than those of the other scenarios. The differences ranged from − 135% to + 98% for the considered circuits in this work. The large differences demonstrate that for accurate estimation of the circuit lifetime under the BTI effect, the dynamic scenario should be adopted as part of the standard design flows.

In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low VTH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the Ion/Ioff ratio of its access transistors, a high VTH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20nm, 16nm, 14nm, 10nm, and 7nm FinFET technologies assuming a supply voltage of 500mV. The results reveal high write and read margins, the highest Ion/Ioff ratio, a fast write, and ultra-low leakage power in the hold "0" state for the cell. Therefore, the suggested 7T cell may be considered as one of the better design choices for both high performance and low power applications. Also, the changes of cell parameters when the temperature rises from -40?C to 100?C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell in the presence of the process variations are studied at two supply voltages of 400mV and 500mV. The study shows that the proposed cell meets the required cell sigma value (6?) under all conditions. Proposing a near-threshold 7T SRAM cell with high read and write stabilities.Presenting a comparative study of the read and hold SNM and write margin (speed).Presenting a comparative study of area, read current, Ion/Ioff, and power.Providing a comparative study of process variation and temperature sensitivity.

Objective To study cutaneous leishmaniasis (CL) for identifying the dominant Leishmania species on CL patients referred to medical health centers of historical Kashan city and suburbs located in Isfahan province in central part of Iran during 2010 to 2011. Methods From 137 CL cases, were microscopically positive, the skin lesion serosity materials of 103 cases were cultured in monophasic culture media (RPMI 1 640). We used the PCR-RFLP method for characterization the Leishmania isolates, by using specific internal transcribed spacer (ITS1) primers and HAEШ as the restriction fast enzyme. DNA was extracted from 63 samples. Results L. tropica is main species in 58 (92.1%) cases and L. major is identified in 5 (7.9%) cases. Indeed randomly two isolates were the species characterized as L. major produced ulcer at the base tail of BALB/c mice after 3 weeks but from three L. tropica isolates none of them produced any lesion during 6 months post inoculation. Conclusions The parasitological, epidemiological aspect and molecular methods of this study showed that, Kashan and suburb are anthroponetic CL area despite this city located in Isfahan province as an ancient focus of zoonotic CL in Iran.

The objective of this paper is to minimize the energy-delay product of static random access memory (SRAM) arrays by using a device-circuit-architecture co-optimization framework. More specifically, at the device-level, high-V t FinFETs are adopted for the 6T SRAM cell, which significantly reduces the leakage power and improves static noise margins. However, due to the lower ON current, the bitline delay of the read access is increased. Accordingly, at the circuit-level, the voltage level of assist circuits, and at the architecture-level (i.e., the array organization), key parameters of the SRAM array are jointly optimized to derive a design that results in the minimum energy-delay product point. By using the proposed optimization framework, for SRAM array capacities ranging from 1KB to 16KB, on average 59% lower energy-delay product with maximum 12% (and on average 9%) performance penalty is achieved.

In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing “0” characteristics of the conventional 8T cell. In addition, a new 10T subthreshold SRAM cell based on FinFET structures which has a lower standby power is suggested. The characteristics of the proposed and conventional 8T and 10T structures in 32 nm planar bulk and FinFET technologies are compared. The results show that the 10T structures have better write characteristics thanks to the differential write and consume less static power while the 8T structures have higher read currents. Also, they reveal that FinFET based structures show better read and write characteristics while consuming less static power with less variation in the presence of process variations.