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This paper introduces two advanced high-power diode packaging designs, respectively named Z-type and A-type from the Zowie Technology Corp., and analyzes temperature and thermo-stress distributions in the two diode packaging structure. To this end, different currents were first provided to the experiments and temperatures on diode surfaces were recorded to extract suitable thermal convective coefficients. The followed simulations were performed and the mechanical behaviors of the two packaging designs are obtained. This paper finally compared the simulation results with discussions.

fcCSP packaging was historically based on solder interconnects. The continued drive towards higher I/O and shrinking package sizes has lead to very dense bump pitches which exceed those of CPUs. At area array bump pitches below 150 um, solder bumps require very complex HDI or ABF-BU substrates which make them unaffordable for the mobile application space. Cu pillars are slim and tall when compared to solder bumps and thereby provide more space between interconnects at the same pitch. This increased space can be utilized on the substrate side to relax the trace pitch and/or to route escape traces between the pillars. The net effect is a simpler and lower cost substrate. The higher stand-off facilitated by the tall pillars allows undermolding which is significantly more cost effective than capillary underfilling. Here, design rules,process flow and reliability data will be presented from volume manufacturing processes. Modeling data for low K die with Cu pillar will be discussed as well.

In this paper, we perform thermal and thermo-stress analyses on diode packaging with both currently used (traditional) and the newly designed (Zowie) structures in a 5W power adapter. To this end, a global-local methodology with ANSYS FEM software were employed with the equivalent material property equations, and temperature distribution measurements were simultaneously carried out for verification and extracting boundary conditions. The simulated mechanical behaviors on the two packaging designs are finally compared with discussions in this study.

To analyze thermal and thermo-stress behaviors of the diode packaging for high power applications, a global-local scheme through finite element simulations are performed in this study. To derive necessary boundary conditions and to verify the simulation results, thermal experiments are carried out for comparisons. New diode packaging designs are next proposed in this paper and their thermal resistance and structure stress are finally compared with the currently used ones to study the improvements.

Flip chip (fc) packaging has been practiced for many years but mainly for high end computer and certain automotive devices. RoHS has driven the conversion from lead-based fc bumps to lead-free (Pb-free) bumps. Pb-free was adopted more readily in consumer and mobile applications than in high reliability applications. A few years back, Intel introduced copper pillars (CuP) as an alternative to high Pb bumps to minimize electro-migration which was found at high currents in high performance applications. CuP was used in conjunction with Pb-free solder thereby achieving compliance with RoHS while at the same time improving reliability with superior electro-migration and thermal performance. Now, mobile applications are adopting CuP but primarily for fine pitch applications. CuPs are invariant in height and diameter during reflow unlike solder bumps which were also termed controlled chip collapse connections (C4). C4s have the advantage of self-aligning during solder reflow i.e. placement accuracy does not have to be extremely precise. With the advent of high precision die bonders, die with CuPs and small solder caps can be placed sufficiently accurate to enable mass reflow connections. CuPs do enable other significant advantages which do enable significant cost reductions. The fixed diameter of the pillars provides a larger pillar to pillar spacing as compared solder bumps at the same pitch and stand-off. The larger spacing which avoids any shorting concerns also potentially allows additional traces between bumps/pillars, thereby increasing the routability. Or alternatively, wider traces/spaces can be employed in the substrate design which equates to simpler substrate processes albeit lower substrate costs. The higher stand-off facilitates mold-only underfill processing which is also a significant process simplification i.e. cost reduction. Of course CuPs also present new challenges due to the very high stiffness, especially when assembled to lowK or ELK dies. Finite Element Modeling (FEM) has provided successful guidelines to overcome the stress induced damage that had been observed initially. Here, the advantages of CuP based fcCSP packaging will be detailed with design rules for pillars and substrates to achieve cost reductions. Further, FEM results and design guides for die CuP bumping will be given and substantiated by stress test results. Finally, a roadmap for CuP-fcCSP will be presented.