1. A 1.8-65 fJ/conv.-step 64 dB SNDR Continuous - Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators
- Author
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Timmermans, Martijn, van Oosterhout, Kyle, Fattori, Marco, Harpe, Pieter J.A., Liu, Yao-Hong, Cantatore, Eugenio, Timmermans, Martijn, van Oosterhout, Kyle, Fattori, Marco, Harpe, Pieter J.A., Liu, Yao-Hong, and Cantatore, Eugenio
- Abstract
This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC works, improving the achievable SNDR. The prototype is designed and implemented in a 65-nm CMOS technology, and occupies an area of 0.0045 mm2. In a 20 kHz bandwidth, the LC-ADC achieves a 64 dB SNDR. Thanks to the proposed techniques a power efficiency of up to 1.8 fJ/conv.-step is achieved for sinusoidal inputs. For sparse biopotential signals, a FoMW as low as 0.9 fJ/conv.-step was measured. This makes the prototype interesting for e.g., biomedical applications that make use of spike-based processing.
- Published
- 2024