50 results on '"Harpe, P.J.A."'
Search Results
2. SAR ADCs for Internet of Things: basics and Innovations
- Author
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Harpe, P.J.A., Goes, Joao, Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2017
3. Ultra-low power analog-digital converters for IoT
- Author
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Harpe, P.J.A., Alioto, Massimo, Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
010302 applied physics ,Ultra low power ,business.industry ,Computer science ,Cycles per instruction ,020208 electrical & electronic engineering ,02 engineering and technology ,Converters ,01 natural sciences ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Key (cryptography) ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,business ,Internet of Things ,Computer hardware ,Voltage reference ,Communication channel - Abstract
This chapter addresses ADCs for IoT nodes, which are needed to digitize sensor information before processing, storage or wireless transmission. ADCs are also required for the radio communication channel. This chapter focusses on successive approximation (SAR) ADCs, a popular architecture for IoT thanks to their high power-efficiency. After deriving requirements for IoT, the design basics of SAR ADCs are discussed, followed by various design examples to illustrate key enabling techniques.
- Published
- 2017
4. An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS
- Author
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Xu, Y., Harpe, P.J.A., Ytterdal, T., Xu, Y., Harpe, P.J.A., and Ytterdal, T.
- Abstract
Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm2. The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm2 fJ/conversion-step.
- Published
- 2017
5. Successive approximation analog-to-digital converters
- Author
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Harpe, P.J.A., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
Successive-approximation register analog-to-digital converters (SAR ADCs) have been around for a long time, but they have recently received a lot of attention due to the advantages of process scaling and recent architectural innovations, leading to improvements in power efficiency and conversion speed. For illustration, Figure 1 shows a collection of data converters in terms of energy per conversion (which is the power consumption P divided by the sampling rate fs) and accuracy, expressed as signal-to-noise-and-distortion ratio (SNDR), based on data from [1]. As one can see, SAR ADCs are very power efficient compared to other architectures for medium accuracies between 40 and 70 dB of SNDR. In terms of speed, SAR ADCs have managed to reach sampling rates of up to 90 GS/s when time interleaved [2]. One of the reasons SAR ADCs are doing so well is because they use simple analog and digital circuits that tend to scale well and benefit from newer process technologies. Moreover, the simple structure often allows operation at reduced supply levels, which can save additional power. In this article, we will discuss the basic design aspects of SAR ADCs and give a short overview of state-of-the-art designs and future trends.
- Published
- 2016
6. A 0.20 mm² 3 nW signal acquisition IC for miniature sensor nodes in 65 nm CMOS
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Harpe, P.J.A., Gao, H., van Dommele, A.R., Cantatore, E., van Roermund, A.H.M., Integrated Circuits, Electrical Engineering, RF, Resource Efficient Electronics, Emerging Technologies, and Center for Wireless Technology Eindhoven
- Subjects
Hardware_INTEGRATEDCIRCUITS - Abstract
Miniature mm3-sized sensor nodes have a very tight power budget, in particular, when a long operational lifetime is required, which is the case, e.g., for implantable devices or unobtrusive IoT nodes. This paper presents a fully integrated signal acquisition IC for these emerging applications. It integrates an amplifier with 32 dB gain and 370 Hz bandwidth that includes positive feedback to enhance input impedance and dc offset compensation. The IC includes also a 10 bit 1 kS/s SAR ADC as well as a clock generator and voltage and current biasing circuits. The overall system achieves an input noise of 27 μVrms, consumes 3 nW from a 0.6 V supply, occupies 0.20 mm2 in 65 nm CMOS, and has a single-wire data interface. The amplifier achieves an noise-efficiency factor (NEF) of 2.1 and the ADC has a figure-of-merit (FoM) of 1.5 fJ/conversion-step. Measurements confirm reliable operation for supplies from 0.50 to 0.70 V and temperatures in the range of 0-85 °C. As an application example, an ECG recording is successfully performed with the system while a 0.69 mm2 photodiode array provides its power supply in indoor lighting conditions.
- Published
- 2016
7. Analog calibration of channel mismatches in time-interleaved ADCs
- Author
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Harpe, P.J.A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
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Applied Mathematics ,Electrical and Electronic Engineering ,Computer Science Applications ,Electronic, Optical and Magnetic Materials - Abstract
This paper presents a method for the on-chip measurement and correction of gain errors, offsets and time-skew errors in time-interleaved ADCs. With the proposed method, the errors can be measured and processed in the digital domain. Then, this information is used to optimize several digitally controlled analog parameters of the circuit, which minimize the effect of aforementioned mismatch errors. After optimization, the digital logic can be switched off completely in order to save power. Simulation results on a full-transistor implementation of the time-interleaved sampling structure show that the channel matching errors can be accurately compensated.
- Published
- 2008
8. A 5.5fJ/conv-step 6.4MS/s 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme
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Ding, M., Harpe, P.J.A., Liu, Y.-H., Büsze, B., Philips, K.J.P., Groot, de, H.W.H., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
Wireless standards, e.g., 802.15.4g, need high-resolution ADCs (>10b) with very low power and MS/s sampling rates. The SAR ADC is well known for its excellent power efficiency. However, its intrinsic accuracy (DAC matching) is limited up to 10 to 12b in modern CMOS technologies [1]. Scaling up the device dimensions can improve matching but it deteriorates power-efficiency and speed. Alternatively, calibrations [2-5] are introduced to correct errors (e.g., comparator offset and capacitor mismatch) and push the SNDR beyond 62dB. However, most of the calibrations [2-4] are implemented off-chip and the power for the calibration circuit is relatively high when implemented on-chip. Foreground calibration [4-5] is an alternative but is sensitive to environmental changes. We report a low-power fully automated on-chip background calibration that uses a redundancy-facilitated error-detection-and-correction scheme. Thanks to the low-power calibration, this ADC achieves an ENOB of 10.4b and a power efficiency of 5.5fJ/conv-step at 6.4MS/S.
- Published
- 2015
9. Technological advances in low-power bioelectronics
- Author
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Harpe, P.J.A., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2015
10. A 0.8V 10b 80kS/s SAR ADC with duty-cycled reference generation
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Liu, M., Harpe, P.J.A., Dommele, van, A.R., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2015
11. A 3nW signal-acquisition IC integrating an amplifier with 2.1 NEF and a 1.5fJ/conv-step ADC
- Author
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Harpe, P.J.A., Gao, H., Dommele, van, A.R., Cantatore, E., Roermund, van, A.H.M., Integrated Circuits, RF, Resource Efficient Electronics, Emerging Technologies, and Center for Wireless Technology Eindhoven
- Abstract
Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.
- Published
- 2015
12. A106nW 10 b 80 kS/s SAR ADC with duty-cycled reference generation in 65 nm CMOS
- Author
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Liu, M., Pelzers, Kevin M.P., van Dommele, A.R., van Roermund, A.H.M., Harpe, P.J.A., Liu, M., Pelzers, Kevin M.P., van Dommele, A.R., van Roermund, A.H.M., and Harpe, P.J.A.
- Abstract
This paper presents a 10 b 80 kS/s SAR ADC with low-power duty-cycled reference generation. It generates a stable reference voltage on chip for the SAR ADC and imparts very good immunity against power supply interference to the ADC. A 0.62 V-VDD 25 nW CMOS reference voltage generator (RVG) is presented, which has only ±1.5% variation over process corners. A duty-cycling technique is applied to enable 10% duty-cycling of the RVG, resulting in negligible power consumption of the RVG compared to that of the ADC. Furthermore, a bi-directional dynamic preamplifier is adopted in the SAR ADC, which consumes about half the power compared with a regular dynamic structure and maintains noise and gain performance. Compared with prior-art low-power ADCs, this work is the first to integrate the reference generation and include it in the power consumption while maintaining a competitive 2.4 fJ/conversion-step FoM. The chip is fabricated in 65 nm CMOS technology.
- Published
- 2016
13. Circuit and method for DAC mismatch error detection and correction in an ADC
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Harpe, P.J.A. and Harpe, P.J.A.
- Abstract
A method comprises sampling an input voltage signal, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining an (N+1) bit code representation for a comparison result, the (N+1) bit code yielding the N bit output signal. On detection of the (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for a most significant bit of the (N+1) bit code by replacing the (N+1) bit code by an alternative (N+1) bit code that yields the same N bit output signal, performing an additional comparison cycle using the alternative (N+1) bit code, determining, using comparison results of the additional comparison cycle and the preceding (N+1)th cycle, a sign of a DAC capacitor mismatch error, and tuning programmable binary scaled calibration capacitors in parallel to a capacitor corresponding to the one of the most significant bits of the (N+1) bit code.
- Published
- 2016
14. A 680nA fully integrated implantable ECG-acquisition IC with analog feature extraction
- Author
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Yan, L., Harpe, P.J.A., Osawa, M., Harada, Y., Tamiya, K., Van Hoof, C., Yazicioglu, R.F., Fujino, L.C., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1µW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.
- Published
- 2014
15. A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios
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Meuleman, G., Harpe, P.J.A., Huang, X., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
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Hardware_INTEGRATEDCIRCUITS ,Hardware_PERFORMANCEANDRELIABILITY - Abstract
This paper describes the design and implementation of a low power IF frequency synthesizer which can be used in 2-tone envelope detection radios [1]. The synthesizer is based on an All-Digital PLL (AD-PLL) architecture. By means of a system noise analysis, overall noise performance is optimized while maintaining low-power operation. A current controlled ring-oscillator is designed, optimized for low-power and low phase-noise. An integer and fractional phase quantiser (PQ) is designed, where the fractional PQ is co-integrated with the oscillator to save power. The DAC, which digitally controls the oscillator, is implemented by a `coarse' and `fine' DAC topology to reduce the resolution requirement. The `fine' DAC resolution is increased by a third-order Delta-Sigma Modulator (DSM) to alleviate matching problems while maintaining monotonicity and keeping the power consumption low. Current division of the `fine' DAC, using a highly-linear current-mirror, enables fine frequency tuning while keeping low bias currents. The chip, consisting of a current controlled oscillator, `coarse' and `fine' DAC and fractional part of the phase quantiser is implemented in a 90 nm CMOS technology. The AD-PLL operates from 10 to 20 MHz and the power consumption (excluding digital loop filter and DSM) is only 19 µW at 20 MHz operation.
- Published
- 2014
16. Low-power ADC design in scaled technologies
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Harpe, P.J.A., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2014
17. An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR
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Harpe, P.J.A., Cantatore, E., Roermund, van, A.H.M., Fujino, L.C., Integrated Circuits, Resource Efficient Electronics, Emerging Technologies, and Center for Wireless Technology Eindhoven
- Subjects
Physics::Instrumentation and Detectors - Abstract
Autonomous wireless sensor nodes for cloud networks require ultra-low-power electronics. In particular, sensor readout interfaces need low-speed high-precision ADCs for capturing, e.g., bio-potential signals, environmental information, or interactive multimedia. For these applications, state-of-the-art SAR ADCs can provide highly power-efficient solutions (
- Published
- 2014
18. A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications
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Vidojkovic, Maja, Huang, Xiongchuan, Wang, Xiaoyan, Zhou, C., Ba, A., Lont, M., Liu, Y.-H., Harpe, P.J.A., Ding, M., Büsze, B., Kiyani, N.F., Kanda, K., Masui, S., Philips, K.J.P., Groot, de, H.W.H., Fujino, L.C., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
SDG 7 - Affordable and Clean Energy - Abstract
The introduction of the IEEE802.15.6 standard (15.6) for wireless-body-area networks signals the advent of new medical applications, where various wireless nodes in, on or around a human body monitor vital signs. Radio communication often dominates the power consumption in the nodes, thus low-power transceivers are desired. Most state-of-the-art low-power transceivers support only proprietary modes with OOK or FSK modulations, and have poor sensitivity or low data rate [1,2]. In this work, a 15.6-compliant transceiver with enhanced performance is proposed. First, the data-rate is extended to 4.5Mb/s to cover multi-channel EEG applications. Second, while a best-in-class energy efficiency of 0.33nJ/b is achieved in the high-speed mode, a dedicated low-power mode reduces the RX power further in low-data-rate operation. Third, a sensitivity 5 to 10dB better than the 15.6 specification is targeted to accommodate extra path loss due to shadowing effects from human bodies.
- Published
- 2014
19. Smart self-interference suppression by exploiting a nonlinearity
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Janssen, E.J.G., Habibi, H., Milosevic, D., Baltus, P.G.M., Roermund, van, A.H.M., Baschirotto, A., Makinwa, K.A.A., Harpe, P.J.A., Integrated Circuits, Signal Processing Systems, RF, and Center for Wireless Technology Eindhoven
- Subjects
Physics ,CMOS ,Amplifier ,RF power amplifier ,Electronic engineering ,Linear amplifier ,Noise figure ,Transfer function ,Leakage (electronics) ,Voltage - Abstract
A 1.8GHz RF amplifier implemented in 0.14um CMOS with frequency-independent blocker suppression is presented. The blocker suppression functionality is obtained by the adaptation of a nonlinear input–output transfer according to the blocker amplitude. Since superposition does not apply to nonlinear transfer functions, the behavior of such a transfer for strong undesired signals is different from the behavior for weak desired signals, which is exploited here. In the presence of a 0 to +11 dBm RF blocker, a voltage gain for weak signals of respectively 7.6–9.4 dB and IIP3 >4 dBm are measured, while the blocker is suppressed by more than 35 dB. In case of no blocker present at the input, the circuit is set to amplifier mode providing 17 dB of voltage gain and an IIP3 of 6.6 dBm while consuming 3 mW. Application areas are coexistence in multi-radio devices and dealing with TX leakage in FDD systems.
- Published
- 2013
20. Time-interleaved SAR and slope converters
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Harpe, P.J.A., Ding, M., Büsze, B., Zhou, C., Philips, K.J.P., Groot, de, H.W.H., Roermund, van, A.H.M., Baschirotto, A., Steyaert, M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Time interleaved ,Computer science ,Calibration (statistics) ,Electronic engineering ,Converters - Abstract
This paper investigates time-interleaved SAR and time-interleaved slope converters, targeting low-power, low-resolution, high-speed applications. Fundamentally, these two architectures can be relatively power-efficient as compared to other architectures. At the same time, complex calibration schemes are not required thanks to their inherent accuracy. The architectures are examined and compared, circuit implementations and measurement results are discussed and an outlook to the future will be given.
- Published
- 2013
21. A 430nW 64nV/square root Hertz current-reuse telescopic amplifier for neural recording applications
- Author
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Song, S., Rooijakkers, M.J., Harpe, P.J.A., Rabotti, C., Mischi, M., Roermund, van, A.H.M., Cantatore, E., Integrated Circuits, Signal Processing Systems, Biomedical Diagnostics Lab, Resource Efficient Electronics, Emerging Technologies, and Center for Wireless Technology Eindhoven
- Abstract
This paper presents a low-power low-noise amplifier for neural recording applications. A single-stage current-reuse telescopic topology is proposed to achieve high DC gain and improve the noise efficiency factor (NEF) while allowing the amplifier to be scaled for high bandwidth sensing applications and/or to achieve lower thermal noise floor. The design is fabricated in a standard 0.18µm CMOS process and occupies an active area of 0.16mm2. Experimental measurements show a 430nW power consumption from a 1.2V supply, a thermal noise floor of 63.8nV/vHz and a corresponding NEF of 1.5.
- Published
- 2013
22. A 5bit 1GS/s 2.7mW 0.05mm^2 asynchronous digital slope ADC in 90nm CMOS for IR UWB radio
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Ding, M., Harpe, P.J.A., Hegt, J.A., Philips, K.J.P., Groot, de, H.W.H., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
A 5bit 1GS/s 0.05mm2 4× time-interleaved asynchronous digital slope ADC in 90nm CMOS for IR UWB radio is presented. New delay cells are introduced to double the speed over prior art, yielding the 250MS/s single-channel slope converter. A self-disabled comparator eliminates static leakage and consumes only 0.25pJ/conversion. A single calibration circuit corrects both offset errors and mismatches in the new delay cells, achieving an ENOB of 4.85bit with 1.5GHz ERBW. This ADC consumes 2.7mW at a 1V supply, enabling a FoM of 93fJ/conversion-step. At 0.8V, it can work at 0.5GS/s. Even compared to the state-of-the-art of well-established architectures, it achieves similar power-efficiency.
- Published
- 2012
23. Automatic generation of layout of arrays of current sources and capacitors
- Author
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Balmaekers, B.M., Harpe, P.J.A., Radulov, G.I., Integrated Circuits, Wideband Data Converters, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2012
24. Time-interleaved SAR and slope converters
- Author
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Harpe, P.J.A., Ding, M., Büsze, B., Zhou, C., Philips, K.J.P., Groot, de, H.W.H., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
This paper investigates time-interleaved SAR and time-interleaved slope converters, targeting low-power, low-resolution, high-speed applications. Fundamentally, these two architectures can be relatively power-efficient as compared to other architectures. At the same time, complex calibration schemes are not required thanks to their inherent accuracy. The architectures are examined and compared, circuit implementations and measurement results are discussed and an outlook to the future will be given.
- Published
- 2012
25. A 3uW fully-differential RF envelope detector for ultra-low power receivers
- Author
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Liempd, van, B.W.M., Vidojkovic, Maja, Lont, M., Zhou, C., Harpe, P.J.A., Milosevic, D., Dolmans, G., Integrated Circuits, RF, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Hardware_INTEGRATEDCIRCUITS - Abstract
A fully differential envelope detector (ED) operating at 2.4GHz is designed in 90nm CMOS technology. The new design uses the common-gate topology to deal with large common-mode input signals through first-order current cancellation. Thereby, a fully differential ultra-low power super-regenerative front-end is enabled. It has a measured output voltage swing of 2.8–127mV and achieves 19.6dB output SNR at sensitivity input level. The circuit consumes 3µW from a 1.2V power supply.
- Published
- 2012
26. A 3.72μW ultra-low power digital baseband for wake-up radios
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Zhang, Y., Chen, Sijie, Kiyani, N.F., Dolmans, G., Huisken, J., Büsze, B., Harpe, P.J.A., Meijs, van der, N.P., Groot, de, H.W.H., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Hardware_INTEGRATEDCIRCUITS - Abstract
In order to minimize power consumption without sacrificing much latency performance, wake-up radios are employed to assist the main radio for low power channel monitoring. This paper presents the design and implementation of an ultra-low power digital baseband (DBB) circuit for a wake-up radio. In a 90nm CMOS process, the circuit running at a 800kHz clock consumes 3.72µW with a standard 1.2V supply voltage, and achieves very good packet detection performance. The circuit is fully functional at 0.6V supply consuming 0.9µW.
- Published
- 2011
27. A 160uW 8-channel active electrode amplifier for EEG monitoring
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Xu, J., Yazicioglu, R.F., Harpe, P.J.A., Makinwa, K.A.A., Van Hoof, C., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Hardware_GENERAL - Abstract
An important drawback of current biopotential monitoring systems is their dependence on gel electrodes, which can dry out, cause skin irritation, and necessitate skilled personnel. These associated drawbacks increase the running costs and significantly hamper their use in consumer healthcare and lifestyle applications. Unfortunately, the use of gel-free, or dry, electrodes increases the electrode-tissue contact impedance, thus exacerbating the effects of interference and cable motion artifacts. A solution is the use of active electrodes, i.e. electrodes in which an amplifier with high input impedance, low noise and good electrode offset rejection is co-integrated. Previous active electrodes employed voltage buffers to facilitate the inter-channel gain matching necessary to achieve high CMRR. However, low-noise buffers consume significant power and due to their lack of gain still require a low-noise and thus power-hungry back-end to keep the total integrated noise at acceptable levels. To reduce the total power dissipation, this paper proposes a biopotential monitoring system based on active electrodes with gain.
- Published
- 2011
28. A 0.37uW 4bit 1MS/s SAR ADC for ultra-low energy radios
- Author
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Harpe, P.J.A., Huang, X., Wang, Xiaoyan, Dolmans, G., Groot, de, H.W.H., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Hardware_INTEGRATEDCIRCUITS - Abstract
This paper presents a 4bit SAR ADC for ultra-low energy radios. It is not obvious to maintain good power-efficiency for low resolution, low data rate ADCs given fixed overhead and scaling limitations. Nevertheless, an excellent FOM of 25fJ/conversion-step is achieved by using a dedicated capacitor implementation, asynchronous dynamic logic, an optimized layout and a reduced power supply. The prototype in a 90nm CMOS technology achieves an ENOB of 3.9bit while operating at 1.024MS/s. The power consumption is only 0.37µW from a 0.7V supply, which is an absolute minimum for 1MS/s ADCs.
- Published
- 2011
29. A 56uW VGA with 5MHz bandwidth and 47dB gain-range in 90nm CMOS
- Author
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Zhou, C., Harpe, P.J.A., Rampu, S., Wang, Xiaoyan, D'Amico, S., Baschirotto, A., Philips, K.J.P., Dolmans, G., Groot, de, H.W.H., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Hardware_INTEGRATEDCIRCUITS - Abstract
This paper presents the design and implementation of a variable gain amplifier with an ultra low-power consumption of 56µW. This is achieved by using sub-threshold operation, 1V power supply and a minimum amount of current branches. After system-level optimization, a gain range of 47dB is implemented with 6dB per step programmability. The SNDR is better than 33dB for all gain settings, while the nominal signal bandwidth is 5MHz. The performance is measured on a test-chip in a 90nm CMOS technology.
- Published
- 2010
30. Smart AD and DA conversion
- Author
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Harpe, P.J.A., Hegt, Hans, Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2010
31. Data-driven noise reduction technique for analog to digital converters
- Author
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Harpe, P.J.A. and Harpe, P.J.A.
- Abstract
A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time [tau]MV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time [tau]MV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.
- Published
- 2014
32. A 680nA ECG acquisition IC for leadless pacemaker applications
- Author
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Yan, L., Harpe, P.J.A., Pamula, V.R., Osawa, M., Harada, Y., Tamiya, K., Van Hoof, C., Yazicioglu, R.F., Yan, L., Harpe, P.J.A., Pamula, V.R., Osawa, M., Harada, Y., Tamiya, K., Van Hoof, C., and Yazicioglu, R.F.
- Abstract
A sub- µW ECG acquisition IC is presented for a single-chamber leadless pacemaker applications. It integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor. To save ASIC power, a current-multiplexed channel buffer is introduced to drive a 7 b-to-10 b self-synchronized SAR ADC which utilizes 4 fF/unit capacitors. The ASIC consumes only 680nA and achieves CMRR >90 dB, PSRR >80 dB, an input-referred noise of 4.9 µVrms in a 130 Hz bandwidth, and has rail-to-rail DC offset rejection. Low-power heartbeat detections are evaluated with the help of the ASIC acquiring nearly 20,000 beats across 10 different records from the MIT-BIH arrhythmia database. In the presence of muscle noise, both the average Sensitivity (Se) and Positive Predictivity (PP) show more than 90% when the input SNR >6 dB.
- Published
- 2014
33. A 14mW 500MSPS 59dB SFDR open-loop track-and-hold circuit
- Author
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Harpe, P.J.A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
This paper presents the design and implementation of an open-loop Track-and-Hold circuit in a CMOS 0:18¹m technology. Also, experimental measurement results are discussed. The open-loop architecture is motivated by the fact that it can potentially reduce the power consumption, increase the speed of operation and improve the portability to new process generations. The limited linearity, related to open-loop structures, is improved by applying a combination of three linearization techniques: source degeneration and cross-coupling of the output buffer and clock-boosting of the sampling switches. The simulation and measurement results reveal that the presented T&H achieves a high sampling speed of 500MSPS while consuming 14mW at a 1.8V power supply. Because of the linearization techniques, an SFDR of 59dB is obtained. Moreover, the simplicity of the open-loop structure allows simple migration to future process generations. Benchmarking reveals that the proposed open-loop architecture provides a suitable solution for state-of-the-art AD converters.
- Published
- 2009
34. A new design flow for receiver performance optimization
- Author
-
Deng, W., Mahmoudi, R., Harpe, P.J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
The lack of a systematic design strategy that can monitor the relation between radio frequency (RF) blocks and analog to digital converter (ADC) is one of the main obstacles for achieving overall system optimization. This paper presents a systematic design flow for mixed signal front-end, based on the translation of ADC parameters into the RF domain. This design flow indicates four variables that can be used for the trade-off between RF and ADC blocks.
- Published
- 2008
35. Digital Post-Correction of Front-End Track-and-Hold Circuits in ADCs
- Author
-
Harpe, P.J.A., Zanikopoulos, A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Computer Science::Hardware Architecture - Abstract
This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique.
- Published
- 2006
36. Power Optimization for Pipelined ADCs
- Author
-
Zanikopoulos, A., Harpe, P.J.A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Hardware_INTEGRATEDCIRCUITS ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION - Abstract
The developments over the last years in portable and wireless communications have increased the demand for low power circuits and systems. Analog-to-digital converters (ADCs), as essential parts of these systems, should comply with this low power consumption trend. The pipelined ADC in particular is one of the most popular ADC architectures, because it exhibits very good speed and power consumption capabilities and can be easily implemented in digital CMOS technologies. Therefore a systematic study of power optimization for pipelined ADCs became necessary.
- Published
- 2006
37. Digital Post-Correction of Open-Loop Track-and-Hold Circuits
- Author
-
Harpe, P.J.A., Zanikopoulos, A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
The front-end track-and-hold (T&H) circuit is one of the most critical components of an analog-to-digital converter (ADC). Considering a pipelined ADC, it is known that the errors of each stage of the pipeline will be attenuated by the interstage amplifiers, however, the errors of the front-end T&H will be directly present in the output codes produced by the ADC. Because of this, the accuracy requirements for the front-end T&H are the most stringent of all sample-and-hold stages in the ADC. Recently, the design of open-loop T&H circuits is getting more and more attention. Advantages of open-loop circuits include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. However, a major disadvantage of open-loop circuits is their relatively poor linearity. Therefore, unless some correction technique is applied, the use of open-loop architectures is limited to converters with a low accuracy (up to 8-bit). Though some digital correction techniques for the improvement of the linearity of open-loop structures have been presented previously [1], [2], they are limited to specific implementations or spe- ci¯c types of non-linearity (e.g. third order distortion). In this paper, a general digital post-correction method is presented. This method improves the linearity of the front-end T&H circuit in the digital domain independent on the actual T&H design or the shape of the non-linearity. The method includes both a measurement procedure to determine the actual non-linearity and a correction algorithm. As it is not relying on accurate reference components, it can be integrated easily on-chip. The method was verified by simulations on a T&H circuit designed on transistor-level in a 0:18¹m technology, and shows that its linearity can be improved from 9.5-bit up to 13.5-bit, while operating at a sample frequency of 500MHz.
- Published
- 2006
38. Reliable Design of Digital-to-Analog Converters using Pre-Correction and Embedded Self-Test
- Author
-
Harpe, P.J.A., Meulmeester, de, J.M., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2005
39. Self-Adjusting Bias Current Technique in Flexible ADCs for Mixed-signal SoC Platforms
- Author
-
Zanikopoulos, A., Harpe, P.J.A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2005
40. Digital Pre-Correction Method for Mismatch in DACs with Built-in Self-Measurement
- Author
-
Harpe, P.J.A., Meulmeester, de, J.M., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Published
- 2005
41. A Flexible ADC Approach for Mixed-signal SoC Platforms
- Author
-
Zanikopoulos, A., Harpe, P.J.A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
Time-to-market pressure and increased design complexity created what is called a "design gap" [1] in the design of systems-on-chip (SoC). As a solution to that problem the Platform-Based Design (PBD), based on the design-reuse methodology, has been proposed [2], and successfully applied to digital systems. However, nowadays, the analog part of SoC does not take advantage of PBD and therefore dominates the overall design time, cost and risk. In this paper we propose a Mixed-signal FPGA (FPMA) platform as a solution to the problems described above. Specifically, we address the feasibility of a flexible reprogrammable/reconfigurable ADC platform based on the pipelined architecture. We discuss the programmability issues with respect to the performance-flexibility trade-offs, we justify our decisions and we demonstrate several possible ADC architectures.
- Published
- 2005
42. Digital self-correction of time-interleaved ADCs
- Author
-
Harpe, P.J.A., Zanikopoulos, A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
A well known problem of time-interleaved analogto-digital converters is the matching between the individual channels of the converter. Any mismatch between the channels affects the accuracy of the converter adversely. The random mismatch between the channels originates mainly from the mismatch of components like transistors and capacitors. To achieve a certain degree of matching between the channels, the sizes of the individual components have to be chosen accordingly. Especially for high-resolution converters, this means that physically large transistors are required, resulting in a large chip area, increased power consumption and reduced conversion speed. Instead of increasing sizes to achieve a certain accuracy, one can also start with an analog circuit that is relatively inaccurate from itself (allowing physically small devices), and use a digital post-correction technique afterwards to correct for the actual deviations of each component. With this method, a high accuracy can be obtained while the requirements for the components are relaxed significantly. Although these techniques have been available for single-channel converters for many years, techniques correcting the mismatch between several channels are scarce. In this paper, an existing algorithm for single-channel pipelined converters is extended to include inter-channel correction as well, requiring almost no additional hardware.
- Published
- 2005
43. Smart AD and DA Converters
- Author
-
Roermund, van, A.H.M., Hegt, J.A., Harpe, P.J.A., Radulov, G.I., Zanikopoulos, A., Doris, K., Quinn, P.J., Integrated Circuits, Wideband Data Converters, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
In this paper, a concept is proposed to solve the problems related to the embedding of AD and DA converters in system-on-chips, FPGAs or other VLSI solutions. Problems like embedded testing, yield, reliability and reduced design space become crucial bottlenecks in the integration of high-performance mixed-signal cores in VLSI chips. On the other hand, a trend of increasing digital processing power can be observed in almost all these systems. The presented smart approach takes full advantage of this trend in order to solve the before mentioned problems and to achieve true system integration.
- Published
- 2005
44. Design Strategy for a Pipelined ADC Employing Digital Post-correction
- Author
-
Harpe, P.J.A., Zanikopoulos, A., Hegt, J.A., Roermund, van, A.H.M., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
This paper describes how the usage of digital post-correction techniques in pipelined analog-to-digital converters (ADC's) can be exploited optimally during the design-phase of the converter. It is known that post-correction algorithms reduce the influence of several cir- cuit impairments on the final accuracy of the converter [1], [2]. However, until now, no models relating these circuit impairments to the final accuracy of the ADC, taking the usage of a post-correction algorithm into account, have been known to exist. To take maximum advantage of a certain correction algorithm, this model is a must. Therefore, this paper introduces a behavioral model of a pipelined ADC, including several important error mechanisms, representing possible circuit impairments like offset, gain error, harmonic distortion, etc. With this model, including the post-correction algorithm, simple design con- straints for each part of the circuit can be derived such that a certain target accuracy of the ADC is achieved. In the analog design-phase these high-level constraints can be translated to implementation-dependent low-level design requirements. If these low-level requirements are fulfilled, the model guarantees that the converter will achieve its target accuracy. A design-example for a 12-bit pipelined ADC is worked out. Simulation results will be shown, validating the correctness of the presented design-method. The proposed design-strategy can be applied to all pipelined ADC's with post-correction like in [1], [2], taking maximum advantage of the benefits of the correction algorithm during the analog design-phase.
- Published
- 2004
45. Concepts for smart AD and DA converters
- Author
-
Harpe, P.J.A. and Harpe, P.J.A.
- Abstract
This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed
- Published
- 2010
46. An alternative design flow for receiver performance optimization through a trade-off between RF and ADC
- Author
-
Deng, W., Mahmoudi, R., Harpe, P.J.A., Roermund, van, A.H.M., Deng, W., Mahmoudi, R., Harpe, P.J.A., and Roermund, van, A.H.M.
- Abstract
The lack of a systematic design strategy that can monitor the relation between RF blocks and ADC is one of the main obstacles for achieving overall system optimization. This paper presents an alternative design flow based on the translation of ADC parameters into the RF domain. This design flow indicates four variables that can be used for the trade-off between RF and ADC blocks. Associating these key variables to power consumption enables the trade-off between the block performance and system power consumption. The demonstrated capability of this method is illustrated by comparing two scenarios, related to the IEEE 802.11a standard.
- Published
- 2008
47. Design of a high-speed, high-resolution pipelined AD converter
- Author
-
Harpe, P.J.A. and Harpe, P.J.A.
- Published
- 2004
48. Asynchronous digital slope analog-to-digital converter and method thereof
- Author
-
Harpe, P.J.A., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Abstract
The present invention is related to an analog to digital converter circuit (1). The converter circuit comprises at least one input node (2) for applying an analog input voltage signal (V in ), sampling means (3) for sampling said analog input voltage signal, a first array of capacitors (5) arranged for receiving the sampled analog input voltage signal (4), a digital delay line (6) connected to the first array of capacitors (5) and arranged for being enabled by a clock generator (7) and for generating a staircase or slope function by means of the first capacitor array, taking into account the sampled analog input voltage signal, a comparator (8) arranged for comparing a converted signal (9) with a reference voltage (V ref ), said converted signal being a version of said sampled analog input voltage (4) converted according to said staircase or slope function, and for generating a stop signal (10) based on the comparison result thereby latching the digital delay line and thereby acquiring the digital code.
- Published
- 2011
49. Noise-shaping device and method with improved losless compression and good audio quality for high fidelity audio
- Author
-
Reefman, D., Harpe, P.J.A., Janssen, E.E., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Data_CODINGANDINFORMATIONTHEORY - Abstract
Improved sigma-delta modulator (SDM) for 1-bit digital audio noise shaping. It is the object to produce a bit stream that is compatible with the Scarlet Book specification (Super Audio CD standard, SACD) and that achieves a higher lossless compression ratio when compressed and decompressed according to the standard. This goal is achieved by using a trellis-based SDM and/or a prediction filter within the SDM that is similar or identical to the prediction filter in the encoder. The trellis SDM is designed to produce a predicted signal from a range of candidate signals that is as close to the input signal as possible.
- Published
- 2007
50. Noise-shaping device and method with improved losless compression and good audio quality for high fidelity audio
- Author
-
Reefman, D., Harpe, P.J.A., Janssen, E.E., Integrated Circuits, Resource Efficient Electronics, and Center for Wireless Technology Eindhoven
- Subjects
Data_CODINGANDINFORMATIONTHEORY - Abstract
Improved sigma-delta modulator (SDM) for 1-bit digital audio noise shaping. It is the object to produce a bit stream that is compatible with the Scarlet Book specification (Super Audio CD standard, SACD) and that achieves a higher lossless compression ratio when compressed and decompressed according to the standard. This goal is achieved by using a trellis-based SDM and/or a prediction filter within the SDM that is similar or identical to the prediction filter in the encoder. The trellis SDM is designed to produce a predicted signal from a range of candidate signals that is as close to the input signal as possible.
- Published
- 2006
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