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High mobility materials (such as SiGe, Ge and III-V) are attractive replacements for the conventional Si channel material in future CMOS technology nodes (

Superconducting qubits have made great strides over the past decade, as evidenced by the announcement of 17-qubit and 50-qubit chips towards the end of 2017. The promise of quantum computing for solving problems of interest to society (such as complex drug design, and cryptography for national security, etc.) can be significantly advanced by the fabrication of qubits with high performance characteristics that faithfully replicate the designer's intent. Additionally, energy-efficient ways with low latency to control qubits at millikelvin temperatures are being researched. Superconducting digital electronics are one such approach, which can be 3D-integrated with qubits, with appropriate care taken to avoid quasi-particle poisoning of qubits. In this presentation, the potential advantages and challenges of qubit and superconducting electronics fabrication using advanced 300mm wafer processes will be discussed, followed by a review of millikelvin characterization results from qubits fabricated using 193nm lithographic techniques on 300mm wafers. The selection of materials, and formation of high quality interfaces during the fabrication of superconducting structures will be discussed, along with high resolution transmission electron microscopy and other analyses that guide such process development – these serve to illustrate the potential for achieving further increases in coherence time and qubit frequency control through the use of advanced 300mm fabrication and characterization techniques. The development of ‘manufacturing-friendly’ qubit architectures is essential to enable the creation of well-controlled qubits, as would be required to tackle practical computational problems of interest. Some of the approaches to ‘manufacturing-friendly’ qubit fabrication under consideration at SUNY Poly will be discussed, along with their 3D integration with control circuits and readout mechanisms.

We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowing uniform current collection perpendicularly through the sidewall of the contact. We demonstrate statistically significant specific contact resistivity (ρc) extraction of 2×10-8Ω cm2 and 5×10-9Ω cm2 for n-type and p-type NiSi contacts, respectively, on a 300-mm wafer, which are about 50% less than those extracted using the conventional TLM structure. The proposed structure also shows a tighter distribution in the extracted ρc values. The results show the importance of such test structures to accurately extract ultralow ρc values relevant to sub-14-nm technology nodes.

Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is developed to derive BERs as functions of the design margin, to provide guidance for technology evaluation and product design. The proposed BER calculation can also be used in the off-line bench test and build-in-self-test (BIST) for adaptive error correction and for the other types of random access memories., Comment: 4 pages. Memory Workshop (IMW), 2015 IEEE International

In this work, we report high performance (I on ∼1 mA/µm at Ioff 100nA/µm @ 1V Vcc) short channel p-type SiGe/Si FinFETs combining high mobility, low T inv (scaled High-k w/o Si cap), low R sd , and process-induced strain. A dual channel scheme for high mobility CMOS FinFETs is demonstrated.

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