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The Horizon 2020 (H2020) Future Emerging Technologies (FET) OPEN Project E.T.PACK is dedicated to advancing Electrodynamic Tether (EDT) technology by developing a specialized Deorbit Device prototype for end-of-life satellite deorbiting. In collaboration with the E.T.PACK consortium, the University of Padova conducted test campaigns aimed at evaluating the Deployment Mechanism design. This paper offers an overview of these tests, with a specific emphasis on the outcomes derived from tape spool examinations and deployment tests conducted on specific tape lengths. Furthermore, the paper delineates the setup for upcoming end-to-end deployment tests, highlighting the integration of a tape collecting machine to minimize manual intervention. The three-coil spool successfully passed qualification tests under thermal-vacuum conditions, exhibiting no instances of cold-welding. Additionally, shaker tests validated the spool ability to withstand launch conditions without requiring additional containment flanges. Furthermore, the Deployment Mechanism demonstrated its proficiency in smoothly deploying tapes with varying characteristics within the desired velocity range. Moreover, the deployment process, following a specific profile, proceeded seamlessly without any complications. Consistent continuity was maintained throughout the deployment processes, with no instances of jams or disruptions observed. These testing outcomes represent a fundamental step in the preparation and testing of the Engineering Qualification Model of the Deployment Mechanism, instilling confidence that subsequent end-to-end deployment tests will progress smoothly. To this end, a specific upside-down configuration will be implemented, and a recollecting machine was designed and manufactured to facilitate tape gathering, ensuring a streamlined and efficient testing process. A description of the end-to-end deployment test setup, including the recollecting machine, is also provided in this paper. • Development of the E.T.PACK Deorbit Device based on electrodynamic tether technology. • The E.T.PACK Device is designed for end-of-life satellite deorbiting. • Test campaigns to evaluate the tape spool and the deployment mechanism design. • The spool passed thermal-vacuum tests and endured shaker tests for launch conditions. • The deployment mechanism showed smooth, uninterrupted deployment at target velocities. [ABSTRACT FROM AUTHOR]

Background: Large Language Models (LLMs) are emerging as promising tools in hardware design and verification, with recent advancements suggesting they could fundamentally reshape conventional practices. Objective: This study examines the significance of LLMs in shaping the future of hardware design and verification. It offers an extensive literature review, addresses key challenges, and highlights open research questions in this field. Design: in this scoping review, we survey over 360 papers most of the published between 2022 and 2024, including 71 directly relevant ones to the topic, to evaluate the current role of LLMs in advancing automation, optimization, and innovation in hardware design and verification workflows. Results: Our review highlights LLM applications across synthesis, simulation, and formal verification, emphasizing their potential to streamline development processes while upholding high standards of accuracy and performance. We identify critical challenges, such as scalability, model interpretability, and the alignment of LLMs with domain-specific languages and methodologies. Furthermore, we discuss open issues, including the necessity for tailored model fine-tuning, integration with existing Electronic Design Automation (EDA) tools, and effective handling of complex data structures typical of hardware projects. Conclusions: this survey not only consolidates existing knowledge but also outlines prospective research directions, underscoring the transformative role LLMs could play in the future of hardware design and verification. [ABSTRACT FROM AUTHOR]

Modern technology is relying on hardware accelerators to achieve enhanced performance of computing systems. In the modern computing paradigm, floating point representation of numbers has gained popularity owing to its wide dynamic range. Rounding of floating point numbers to integer is used in modern processor architectures e.g., ARM and Intel's architecture (IA) as well as in specific applications such as multimedia. However, the academic literature lacks discussion on hardware designs for rounding binary floating point numbers to integer in different rounding modes. This article presents novel efficient algorithms and hardware architecture designs for rounding binary floating point numbers to the integer for the following rounding modes: round towards zero, round up (towards positive infinity), round down (towards negative infinity), round to the nearest integer, and round to nearest even. The article also proposes an integrated multi-mode rounding (IMR) algorithm and hardware design which can be configured to a specific rounding mode among the above-mentioned five modes. This article proposes a mantissa bit of rounding (MBR) to determine the condition of rounding for the various modes. The MBR is identified on the basis of the dynamic range and precision features of floating point representation. To the best of our knowledge, we present the individual as well as an integrated hardware design for the various rounding modes for the first time in the literature. The proposed designs have been implemented on an FPGA platform to analyze the design metrics such as area, delay, and power. The results imply that the proposed designs are suitable to aid the intended hardware accelerators as they are efficient in terms of the design parameters. Moreover, this article presents the integration of the proposed rounding hardware design with the compression processor and evaluates the integration overhead which is found to be nominal (<1%). [ABSTRACT FROM AUTHOR]

Copyright of Machine Tool & Hydraulics is the property of Guangzhou Mechanical Engineering Research Institute (GMERI) and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of China Petroleum Machinery is the property of China Petroleum Machinery Editorial Department and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This research presents the design and implementation of an Internet of Things (IoT)-based solution to measure the percentage of Liquefied Petroleum Gas (LPG) inside domestic stationary tanks. The IoT-based sensor, in addition to displaying the percentage of the LPG level in the tank to the user through a mobile application (app), has the advantage of simultaneously sharing the acquired data with an LPG filling plant via the Internet. The design process and calculations for the selection of the electronic components of the IoT-based sensor are presented. The methodology for obtaining and calibrating the measurement of the tank filling percentage from the magnetic level measurement system is explained in detail. The operation of the developed software, and the communication protocols used are also explained so that the data can be queried both in the user's app and on the gas company's web platform safely. The use of the Clark and Wright savings algorithm is proposed to sufficiently optimize the distribution routes that tank trucks should follow when serving different home refill requests from customers located in different places in a city. The experimental results confirm the functionality and viability of the hardware and software developed. In addition, by having the precise location of the tank, the generation of optimized gas refill routes for thirty customers using the heuristic algorithm and a visualization of them on Google Maps is demonstrated. This can lead to competitive advantages for home gas distribution companies. [ABSTRACT FROM AUTHOR]

In the domain of field robotic system, it must deal with several challenges during both design and development durations. This study aims to investigate the whole design of robotic system for the internal inspection of tube. Firstly, the robot configuration is launched to identify the physical dimensions. Owing to the size of tube and the curved trajectory, the estimated parameters and shape of robot could be known. Also, some thresholds are obtained in this design which allows the range of dimensions. Secondly, the kinematic robot is analyzed to compute the flexible motion. Through theoretical computations, its locomotion could be evaluated directly. To realize our design, thirdly the detailed selection of servo motor is introduced in order to provide the powerful drive. Hence, the result of driving computations is shown due to the practical specifications of motor. Correspondingly, the spring which plays a role as damper, is measured to suppress the required torques. This spring ensures the continuous contact between leg of robot and internal wall of tube. As a result of these evaluations, both computer-based model and real-world model have been experimented. To guarantee the effectiveness and feasibility of our approach, three levels of validations are presented. In the numerical simulation, the virtual environment is established to substantiate the robotic locomotion. For the laboratory validation, the hardware robot is confirmed the working abilities as well as some trial results. Lastly, this robot must be exemplified in the real scene such as factory or site construction. From these achievements, it could be obviously seen that our approach is proper and feasible for many applications.

Abstract Diabetic Peripheral Neuropathy (DPN) is a nerve damage that is treated with painkillers and steroids which have the drawback of interference with other medications and the dangers of side effects. Novelty of the proposed work is to develop a Near Infrared Region (NIR) based non-invasive therapy device called ‘DPNrelief-1.0V’developed with a 890 nm wavelength diodes. DPNrelief-1.0V delivers a total dosage of 6.174 J/cm2 with heat absorption by tissue of 61.74 Joules at 30 minutes. The device was tested by carrying out a pilot study with 8 patients where 4 were treatment group and control group. The DPNrelief-1.0V is validated by Nerve Conduction Study (NCS) test. The degenerated nerves pre-therapy showed less amplitude, Conduction Velocity (CV) and latency which was improved post-therapy by 100% in amplitude of nerve signal, 100% in CV and a decrease of 36.2% in latency. Independent t-test was conducted to find the difference between control and treatment, wherein a p value

Diabetic Peripheral Neuropathy (DPN) is a nerve damage that is treated with painkillers and steroids which have the drawback of interference with other medications and the dangers of side effects. Novelty of the proposed work is to develop a Near Infrared Region (NIR) based non-invasive therapy device called ‘DPNrelief-1.0V’developed with a 890 nm wavelength diodes. DPNrelief-1.0V delivers a total dosage of 6.174 J/cm2 with heat absorption by tissue of 61.74 Joules at 30 minutes. The device was tested by carrying out a pilot study with 8 patients where 4 were treatment group and control group. The DPNrelief-1.0V is validated by Nerve Conduction Study (NCS) test. The degenerated nerves pre-therapy showed less amplitude, Conduction Velocity (CV) and latency which was improved post-therapy by 100% in amplitude of nerve signal, 100% in CV and a decrease of 36.2% in latency. Independent t-test was conducted to find the difference between control and treatment, wherein a p value < 0.05 was obtained depicting significant difference between two groups. Furthermore, the performance of the device is validated by one-way test repeated measures Analysis of Variance (ANOVA), wherein a p value of < 0.05 was obtained depicting a difference in nerve condition pre-and post-therapy. The performance of DPNrelief-1.0V has outperformed Anodyne therapy device with lesser dosage, treatment time and portability and in curing the symptoms of DPN. DPNrelief-1.0V finds its potential in the field of medicine for treating DPN. [ABSTRACT FROM AUTHOR]

In order to effectively reduce the failure rate of vibrating screens, a vibration monitoring system design was proposed based on the structure and working principle. The system should be able to monitor the operating state of the vibrating screen in real time, including vibration amplitude, frequency, axial displacement, etc., and be able to detect abnormal conditions in time and give warning prompts. The key hardware of the monitoring system was designed, including acceleration sensor, power module, signal filtering circuit, etc. The sensitivity of the acceleration sensor was measured using comparative method and accurately completed parameter calibration. The eccentric block was used to simulate different deviation of excitation force for system vibration signal test and calibration. The results show that under normal operating conditions, the amplitude of each frequency of the vibrating screen is less than 0.04 g. Under the condition of excitation force deviation, the amplitude of 16 Hz is obviously lower than that of other frequencies, which means that the vibrating screen is currently experiencing lateral oscillation. [ABSTRACT FROM AUTHOR]

Dining with people improves our lives and brings a lot of benefits. Nonetheless, many people are compelled to eat by themselves due to the current social situation. We believe that robots can be good meal partners. In this paper, we describe the developed meal partner robots called Mamoru'21 and Mamoru'22. The design of these robots is inherited from a robot for watching over elderly people. Based on previous research that robot's eating behavior expression can improve the mealtime experience, they can perform motions that mimic eating and present food images by monitors. In the first experiment, we confirmed the developed robot could improve the co-eating experience compared to a conventional small humanoid robot, and investigated the keywords for preferable hardware design, such as 'smaller than a child.' In the second experiment, we studied the effects of the robot's moving around during mealtime. As a result, no statistically significant negative effects of robot movement during meals were observed in the developed robot's capability. Though this study has some limitations such as shorter experimentation time compared to regular meals, it contributes some insights and knowledge into the behavior and design of meal partner robots. [ABSTRACT FROM AUTHOR]

To enhance compression efficiency, the AV1 video coding standard has introduced several new intra-prediction modes, such as smooth and finer directional prediction modes. However, this addition increases computational complexity and hinders parallelized hardware implementation. In this paper, a hardware-friendly rough mode decision (RMD) algorithm and its fully pipelined hardware architecture design are proposed to address these challenges. For algorithm optimization, firstly, a novel directional mode pruning algorithm is proposed. Then, the sum of absolute transform differences (SATD) cost accumulated approximation method is adopted during the tree search. Finally, in the reconstruction stage, a reconstruction approximation model based on the DC transform is proposed to solve the low-parallelism problem. For hardware architecture design, the proposed fully pipelined hardware architecture is implemented with 28 pipeline stages. This design can process multiple prediction modes in parallel. Experimental results show that the proposed fast algorithm achieves 46.8% time savings by 1.96% Bjøntegaard delta rate (BD-Rate) increase on average under all-intra (AI) configuration. When synthesized under the 28nm UMC technology, the proposed hardware can operate at a frequency of 316.2 MHz with 1113.14 K gate count. [ABSTRACT FROM AUTHOR]

High-Efficiency Video Coding (HEVC) is a video compression standard designed to improve video compression efficiency compared to its predecessor, Advanced Video Coding (AVC). HEVC provides approximately twice the compression efficiency compared to the AVC. In the HEVC system, the most computational complexity module is the Motion Estimation (ME). ME module helps reduce redundancy by compensating for motion during video compression. However, the computational complexity makes it a bottleneck in the design of high-resolution video encoders. This paper proposes an efficient architecture for the Integer ME (IME) module of the HEVC encoder. The proposed architecture introduces an efficient memory usage scheme to support the Full Search motion search algorithm. The full pipeline architecture includes 4096 Processing Elements (PE) and an adder tree to compute the Sum of Absolute Difference (SAD) for every Prediction Unit (PU) partition. The proposed architecture was designed and implemented on Xilinx Virtex-7 XC7VX550T FPGA. Our design achieved up to 275 FPS and approximately 10 FPS at 4 K video for the Search Regions of [Formula: see text] and [Formula: see text] pixels, respectively.

Information flow analysis can effectively model the security behavior and security properties of hardware design. However, the existing gate level information flow analysis methods cannot deal with large-scale designs due to computing power and verification effectiveness, and the register transfer level (RTL) information flow analysis methods require formal languages to rewrite hardware designs. This paper proposes a RTL hardware design information flow modeling and security verification method. Based on the RTL functional model, this method develops an information flow tracking logical model to model security behavior and security properties of RTL hardware designs from the perspective of information flow. This method can be integrated into EDA flows and uses EDA testing and verification tools to capture security property violations and detect security vulnerabilities based on non-interference security policy. The results on experiments with Trust-Hub hardware Trojan benchmarks show that the proposed method can effectively detect hardware Trojans.

Electrocardiography (ECG) has emerged as a ubiquitous diagnostic tool for the identification and characterization of diverse cardiovascular pathologies. Wearable health monitoring devices, equipped with on-device biomedical artificial intelligence (AI) processors, have revolutionized the acquisition, analysis, and interpretation of ECG data. However, these systems necessitate AI processors that exhibit flexible configuration, facilitate portability, and demonstrate optimal performance in terms of power consumption and latency for the realization of various functionalities. To address these challenges, this study proposes an instruction-driven convolutional neural network (CNN) processor. This processor incorporates three key features: (1) An instruction-driven CNN processor to support versatile ECG-based application. (2) A Processing element (PE) array design that simultaneously considers parallelism and data reuse. (3) An activation unit based on the CORDIC algorithm, supporting both Tanh and Sigmoid computations. The design has been implemented using 110 nm CMOS process technology, occupying a die area of 1.35 mm2 with 12.94 µW power consumption. It has been demonstrated with two typical ECG AI applications, including two-class (i.e., normal/abnormal) classification and five-class classification. The proposed 1-D CNN algorithm performs with a 97.95% accuracy for the two-class classification and 97.9% for the five-class classification, respectively. [ABSTRACT FROM AUTHOR]

Copyright of Rolling Stock (1002-7602) is the property of Rolling Stock Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper explores advanced techniques in highlevel synthesis (HLS) utilizing metamodel structures. Metamodels act as models of hardware models, generating internal hardware models based on parameter inputs and exploring the solution space to find optimal configurations. The focus is on enhancing HLS processes through metamodeling, enabling more efficient hardware design and optimization. Key contributions include a novel metamodel framework and a case study demonstrating its application in complex system designs. The proposed methods show significant improvements in synthesis efficiency and scalability, making them highly relevant for modern FPGA and ASIC design workflows.

This research presents the design and implementation of an Internet of Things (IoT)-based solution to measure the percentage of Liquefied Petroleum Gas (LPG) inside domestic stationary tanks. The IoT-based sensor, in addition to displaying the percentage of the LPG level in the tank to the user through a mobile application (app), has the advantage of simultaneously sharing the acquired data with an LPG filling plant via the Internet. The design process and calculations for the selection of the electronic components of the IoT-based sensor are presented. The methodology for obtaining and calibrating the measurement of the tank filling percentage from the magnetic level measurement system is explained in detail. The operation of the developed software, and the communication protocols used are also explained so that the data can be queried both in the user’s app and on the gas company’s web platform safely. The use of the Clark and Wright savings algorithm is proposed to sufficiently optimize the distribution routes that tank trucks should follow when serving different home refill requests from customers located in different places in a city. The experimental results confirm the functionality and viability of the hardware and software developed. In addition, by having the precise location of the tank, the generation of optimized gas refill routes for thirty customers using the heuristic algorithm and a visualization of them on Google Maps is demonstrated. This can lead to competitive advantages for home gas distribution companies.

Convolutional neural networks (CNNs) have demonstrated remarkable performance in many areas but require significant computation and storage resources. Quantization is an effective method to reduce CNN complexity and implementation. The main research objective is to develop a scalable quantization algorithm for CNN hardware design and model the performance metrics for the purpose of CNN implementation in resource-constrained devices (RCDs) and optimizing layers in deep neural networks (DNNs). The algorithm novelty is based on blending two quantization techniques to perform full model quantization with optimum accuracy, and without additional neurons. The algorithm is applied to a selected CNN model and implemented on an FPGA. Implementing CNN using broad data is not possible due to capacity issues. With the proposed quantization algorithm, we succeeded in implementing the model on the FPGA using 16-, 12-, and 8-bit quantization. Compared to the 16-bit design, the 8-bit design offers a 44% decrease in resource utilization, and achieves power and energy reductions of 41% and 42%, respectively. Models show that trading off one quantization bit yields savings of approximately 5.4K LUTs, 4% logic utilization, 46.9 mW power, and 147 μ J energy. The models were also used to estimate performance metrics for a sample DNN design. [ABSTRACT FROM AUTHOR]

The typical Integrated Circuit (IC) development process commences with formulating specifications in natural language and subsequently proceeds to Register Transfer Level (RTL) implementation. RTL code is traditionally generated through manual efforts, using Hardware Description Languages (HDL) such as VHDL or Verilog. High-Level Synthesis (HLS), on the other hand, converts programming languages to HDL; these methods aim to streamline the engineering process, minimizing human effort and errors. Currently, Electronic Design Automation (EDA) algorithms have been improved with the use of AI, with new advancements in commercial (such as ChatGPT, Bard, among others) Large Language Models (LLM) and open-source tools presenting an opportunity to automate the chip design process. This paper centers on the creation of AI by AI, a Convolutional Neural Network (CNN) IC entirely developed by an LLM (ChatGPT-4), and its manufacturing with the first fabricable open-source Process Design Kit (PDK), SKY130A. The challenges, opportunities, advantages, disadvantages, conversation flow, and workflow involved in CNN IC development are presented in this work, culminating in the manufacturing process of AI by AI using a 130 nm technology, marking a groundbreaking achievement as possibly the world's first CNN entirely written by AI for its IC manufacturing with a free PDK, being a benchmark for systems that can be generated today with LLMs. [ABSTRACT FROM AUTHOR]

Medical image compression is vital for preserving image quality and optimizing storage and transmission in healthcare facilities. FPGA design faces challenges in balancing compression ratios, speed, and power consumption. This study proposes a novel approach using the Selfish Herd Optimization (SHO) algorithm to cluster medical image data based on anatomical features. A hybrid deep convolutional neural network generates optimal predictors for each cluster, extracting features from the image data and generating predictions for each pixel based on its neighbors. The proposed system achieves low power and high-speed FPGA design while ensuring reliability and accuracy. Experimental results on Virtex-7 VC709 and Virtex-5QV130FX FPGAs demonstrate impressive improvements, including a 244.08% increase in frequency, 210.04% increase in speed, 200.90% increase in throughput, 61.37% increase in efficiency, and significant reductions in resource utilization and power consumption. This design promises efficient lossless medical image compression with enhanced performance. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer-Aided Design & Computer Graphics / Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao is the property of Gai Kan Bian Wei Hui and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The paper presents a practical methodology for the prediction of power consumption of a multitask real-time system. The authors briefly recall the structure of the original multitasking time-predictable system. The system has a regular and scalable architecture. It consists of many cores based on pipeline processing with threads' interleaving mechanism. In previous works, the authors have presented a number of issues related to the methodology of designing a time-predictable system and the scheduling of hardware threads with different design goals and constraints. The current article presents an accurate method for measuring the dynamic power dissipated in a system for various scenarios and the system configuration. The proposed approach is based on continuous monitoring of the power consumed by the FPGA, transmitting the measurements to the computer from the measuring device, and online analysis of the obtained results. The authors based their power estimation method on the original task frequency factor (TF). A theoretical analysis was made, and a series of practical experiments were carried out. The results obtained enable accurate estimation of the power requirements for the tasks performed in the real-time system. The presented technique can be useful during the design stage of multitasking real-time systems. [ABSTRACT FROM AUTHOR]

Lossless compression of medical images can reduce data size, save storage and transmission costs, and cope with the challenge of increasing resolution demand for medical images. This paper proposes an adaptive pipeline hardware architecture for lossless compression/decompression of medical images based on joint photographic experts group-lossless (JPEG-LS), which can achieve efficient image processing on field programmable gate array (FPGA). In addition, by adding a pipeline pause mechanism, the problem of coding errors caused by parameter updates is solved. On the one hand, the binary search method is used to optimize the calculation process of the Golomb coding parameter k in the pipeline, which reduces the parameter update delay. On the other hand, the construction process of the context causal template is optimized, which effectively improves the throughput. Based on the parallel block compression architecture, a hardware module for alpha red green blue (ARGB) image block compression/decompression with customizable block size is implemented, which improves the image compression/decompression throughput and reduces the compression and decompression delay. This paper implements the hardware architecture on Zynq7000 FPGA and evaluates its performance. Compared with existing schemes, the proposed architecture uses less resources and achieves higher compression ratio and clock frequency.

Airborne 3D imaging using ultrasound is a promising sensing modality for robotic applications in harsh environments. Over the last decade, several high-performance systems have been proposed in the literature. Most of these sensors use a reduced aperture microphone array, leading to artifacts in the resulting acoustic images. This paper presents a novel in-air ultrasound sensor that incorporates 1024 microphones, in a 32-by-32 uniform rectangular array, in combination with a distributed embedded hardware design to perform the data acquisition. Using a broadband Minimum Variance Distortionless Response (MVDR) beamformer with Forward-Backward Spatial Smoothing (FB-SS), the sensor is able to create both 2D and 3D ultrasound images of the full-frontal hemisphere with high angular accuracy with up to 70 $\mathrm { \text {dB}}$ main lobe to side lobe ratioin the array response in a single-source scenario. This paper describes both the hardware infrastructure needed to obtain such highly detailed acoustical images, as well as the signal processing chain needed to convert the raw acoustic data into said images. Utilizing this novel high-resolution ultrasound imaging sensor, we wish to investigate the limits of both passive and active airborne ultrasound sensing by utilizing this virtually artifact-free imaging modality.

This study explores the implementation of lightweight binary classification algorithms on low-cost Field-Programmable Gate Arrays (FPGAs) for medical image analysis. Recognizing the growing demand for efficient and accurate diagnostic tools in healthcare, we focus on applying FPGAs to process small-sized medical images, explicitly targeting the detection of malaria from blood cell images. Our approach involves the hardware designs of k-nearest Neighbors (k-NN), Convolutional Neural Networks (CNN), and Decision Tree classifiers rigorously tested on a publicly available Malaria dataset. The methodology emphasizes the integration of these classifiers on FPGA, detailing the optimization strategies that allow for enhanced processing speed and reduced resource utilization. Comparative analysis reveals that our FPGA-based implementation significantly outperforms MATLAB simulations, achieving processing speeds more than thousands of times faster. Our proposed hardware design also requires fewer Look-up Tables (LUTs) than other classification studies in the literature, showcasing decreases of 73.9% for k-NN, 57% for CNN, and 96.7% for the Decision Tree classifier. Furthermore, results highlight the Decision Tree classifier as the most effective, with an accuracy rate of 99.33%, followed by CNN at 97.67% and k-NN at 95.33%. These findings demonstrate the capability of FPGAs in medical image classification and underscore their potential to revolutionize disease diagnosis processes, particularly in resource-limited environments.

Echolocation is the prime sensing modality for many species of bats, who show the intricate ability to perform a plethora of tasks in complex and unstructured environments. Understanding this exceptional feat of sensorimotor interaction is a key aspect into building more robust and performant man-made sonar sensors. In order to better understand the underlying perception mechanisms it is important to get a good insight into the nature of the reflected signals that the bat perceives. While ensonification experiments are an important way to better understand the nature of these signals, they are as time-consuming to perform as they are informative. In this paper we present SonoTraceLab, an open-source software package for simulating both technical as well as biological sonar systems in complex scenes. Using simulation approaches can drastically increase insights into the nature of biological echolocation systems, while reducing the time- and material complexity of performing them.

We propose a hardware-optimized design that implements a Montgomery Elliptic-curve point multiplication Algorithm over $GF(2^{233})$ using Lopez-Dahab projective coordinates. Moreover, we propose a digit-parallel modular multiplier, which reduces clock cycles and improves throughput. Also, we provided how to use our proposed digit-parallel multiplier for post-quantum cryptography algorithms. In addition, we use the proposed digit-parallel multiplier with the square circuit to implement the Itoh-Tsujii inversion algorithm for modular inversion computation; this permits hardware resource minimization. An efficient finite-state machine controller is implemented for control functionalities. A figure of merit in throughput/area is defined for reasonable comparison to state-of-the-art. We provide implementation results after post-place-and-route on field-programmable gate array devices. On the Virtex-7 device, our design utilizes 3386 slices and requires 7218 clock cycles; it achieves a maximum frequency of 365 MHz and computes one point multiplication in $19.77\mu s$ . The total power consumption of our design is 2027 mW. The calculated values for throughput and figure of merit are 50.58Kbps and 14.93, respectively. Consequently, the implementation results and comparisons reveal our design’s suitability for applications requiring area and throughput-optimized cryptographic implementations.

This paper conducts an extensive comparative study of state-of-the-art solutions for implementing the SHA-3 hash function. SHA-3, a pivotal component in modern cryptography, has spawned numerous implementations across diverse platforms and technologies. This research aims to provide valuable insights into selecting and optimizing Keccak SHA-3 implementations. Our study encompasses an in-depth analysis of hardware, software, and software–hardware (hybrid) solutions. We assess the strengths, weaknesses, and performance metrics of each approach. Critical factors, including computational efficiency, scalability, and flexibility, are evaluated across different use cases. We investigate how each implementation performs in terms of speed and resource utilization. This research aims to improve the knowledge of cryptographic systems, aiding in the informed design and deployment of efficient cryptographic solutions. By providing a comprehensive overview of SHA-3 implementations, this study offers a clear understanding of the available options and equips professionals and researchers with the necessary insights to make informed decisions in their cryptographic endeavors. [ABSTRACT FROM AUTHOR]

This paper presents a novel S-box generation scheme to enhance the security of the Advanced Encryption Standard（AES） algorithm. After analyzing the existing issues with S-boxes, a new S-box is constructed based on the principles of S-box construction and its cryptographic properties. This is achieved by selecting new irreducible polynomials and affine transformations while adjusting the order of affine transformations and multiplicative inversion operations. The newly generated S-box is compared with the S-box of AES and other improved S-boxes in terms of algebraic terms and strict avalanche criteria distance. The results demonstrate that the new S-box exhibits superior algebraic properties and effectively defends against algebraic attacks. Furthermore, the new S-box is subjected to hardware design and optimization. The DC synthesis results reveal that the optimized implementation of the new S-box in the finite field consumes 12% fewer resources compared to traditional finite field implementations and 41% fewer resources compared to lookup table methods. This paper substantiates the superiority of the new S-box in terms of security over the existing S-boxes. It also applies the new S-box to AES software and hardware designs, with the correctness of the implementation verified through simulation testing. [ABSTRACT FROM AUTHOR]

This paper reviews hardware-based protection methods for electronic devices, encompassing scientific publications and published patents. This review covers insights from the scientific community and innovative solutions patented in the industry. By combining these two sources, this paper offers a comprehensive and holistic review of electronic device security. Electronic devices are integral to modern life, but their widespread use invites security threats, both digital and physical. This paper reviews hardware-based protection methods against invasive and non-invasive attacks, emphasizing the importance of a dual approach through hardware design. Invasive attacks involve physical tampering, and we explore anti-tampering techniques such as conductive meshes, sensors and physically unclonable functions (PUFs). Non-invasive, side-channel attacks encompass various attack vectors, focusing on electromagnetic analysis. To counter these attacks, we analyze techniques like reducing and masking electromagnetic radiation. This paper bridges the gap between invasive and non-invasive attack mitigation. It underscores the necessity of a multifaceted approach to safeguard electronic devices in an interconnected world, preserving their reliability and functionality. [ABSTRACT FROM AUTHOR]

Among the stereo matching algorithms, the semi-global matching (SGM) is an efficient and high-accuracy method. However, its huge demand for memory access and high computational complexity makes it difficult to achieve a real-time and efficient processing on hardware. Based on the spatial redundancy found in the matching cost, we propose some effective techniques to reduce the requirement of on-chip and off-chip memory, while simultaneously greatly lower the computational complexity. Experimental results present that the proposed SGM algorithm reduces the computational complexity by 71%–74% and has almost the same quality of disparity map compared with the original 8-path SGM. The proposed 3-path fully-pipelined architecture is implemented on the Xilinx VCU-106 with a throughput of 1920 × 1080/54 fps. We also synthesize and layout it with TSMC 40 nm standard library, leading to an area of 8.1 mm 2 with throughput of 1920 × 1080/192 fps. The million disparity estimation per second (MDE/s) of the proposed design reaches up to 50,960, which outperforms conventional ASIC implementations. • We propose two SGM designs using the four-cycle time-sharing structure. • One is 4-path SGM, which has almost the same quality as the original 8-path SGM. • One is 3-path SGM, which completely eliminates the requirement of off-chip memory. • We aimed to lower the hardware complexity and reduce memory access requirements. [ABSTRACT FROM AUTHOR]

This paper presents a throughput/area-efficient hardware accelerator architecture for elliptic curve point multiplication (ECPM) computation over G F (2 233) . The throughput of the proposed accelerator design is optimized by reducing the total clock cycles using a bit-parallel Karatsuba modular multiplier. We employ two techniques to minimize the hardware resources: (i) a consolidated arithmetic unit where we combine a single modular adder, multiplier, and square block instead of having multiple modular operators, and (ii) an Itoh–Tsujii inversion algorithm by leveraging the existing hardware resources of the multiplier and square units for multiplicative inverse computation. An efficient finite-state-machine (FSM) controller is implemented to facilitate control functionalities. To evaluate and compare the results of the proposed accelerator architecture against state-of-the-art solutions, a figure-of-merit (FoM) metric in terms of throughput/area is defined. The implementation results after post-place-and-route simulation are reported for reconfigurable field-programmable gate array (FPGA) devices. Particular to Virtex-7 FPGA, the accelerator utilizes 3584 slices, needs 7208 clock cycles, operates on a maximum frequency of 350 MHz, computes one ECPM operation in 20.59 μ s, and the calculated value of FoM is 13.54. Consequently, the results and comparisons reveal that our accelerator suits applications that demand throughput and area-optimized ECPM implementations. [ABSTRACT FROM AUTHOR]

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In the sensorless control algorithm of permanent magnet synchronous motors (PMSMs), there is a significant research focus on developing a high-performance position observer and a cost-effective, high-performance processor specifically designed for PMSMs. In this paper, we first reviewed the current mainstream position observation algorithms. Subsequently, we proposed a position observation algorithm based on a fixed-point nonlinear flux linkage model that introduces a variable gain model and an observer compensation model. Furthermore, we implemented the improved position observation algorithm in the circuit and designed a System-on-Chip (SOC) suitable for the sensorless control of high-speed permanent magnet synchronous motors using the ARM Cortex-M0 core. The functionality of the proposed SOC was verified on the Field Programmable Gate Array (FPGA) platform. The results demonstrate that the improved algorithm offers an excellent angle observation accuracy and fast convergence speed. The error between the observed angle and the actual angle is less than 0.2 rad. Additionally, the designed SOC balances the high efficiency of hardware implementation with the flexibility of software implementation. When running a sensorless control algorithm for PMSM, it achieves a 30.3% increase in execution efficiency, enabling support for higher frequency output PWM switching and making it suitable for the high-precision control of high-speed PMSM. [ABSTRACT FROM AUTHOR]

As an essential protection mechanism of information security, hash algorithms are extensively used in various security mechanisms. The diverse application scenarios make the implementation of hash algorithms more challenging regarding flexibility, performance, and resources. Since the existing studies have such issues as wasted resources and few algorithms are supported when implementing hash algorithms, we proposed a new reconfigurable hardware architecture for common hash algorithms in this paper. First, we used the characteristics of symmetry of SM3 (Shang Mi 3) and SHA2 (Secure Hash Algorithm 2) to design an architecture that also supports MD5 (Message Digest 5) and SHA1 (Secure Hash Algorithm 1) on both sides. Then we split this architecture into two layers and eliminated the resource wastes introduced by different word widths through exploiting greater parallelism. Last, we further divided the architecture into four operators and designed an array. The experimental results showed that our architecture can support four types of hash algorithms successfully, and supports 32-bit and 64-bit word widths without wasting resources. Compared with existing designs, our design has a throughput rate improvement of about 56.87–226% and a throughput rate per resource improvement of up to 5.5 times. Furthermore, the resource utilization rose to 80% or above when executing algorithms. [ABSTRACT FROM AUTHOR]