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Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs' output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only 60 μm by 1900 μm which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.

Mass-storage systems made of multi-level cell (MLC) NAND flash memory are cost effective but suffer from limited sequential write throughput. Although conventional interleaved write scheme helps, the unique characteristic of the MLC that the write time of a least significant bit (LSB) is much shorter than that of a most significant bit (MSB) leaves performance improvement headroom. This article presents an interleaved write scheme for improving the sequential write throughput of the multi-chip MLC NAND flash memory system. It leverages the longer write time of the upper pages to transmit more data by reordering the interleaved write sequence of the MLC chips. The proposed scheme can be directly implemented in the firmware of the flash memory controller without conflicting with existing flash translation layer (FTL) routines. No hardware modification is needed. The design criteria and performance improvements of general MLC NAND flash storage systems are derived for optimizing the system’s performance. Experimental results of an example single-channel 4-chip solid-state drives (SSD) system showed the sequential write throughput was improved by over 11.4%. The proposed interleaved write scheme can be applied to multi-channel storage systems to improve their sequential write throughput as well.

This letter proposes a novel reference clock free, delay-based coherent binary phase-shift keying (BPSK) demodulator suitable for biomedical devices which receive power and data through the same wireless link. The proposed BPSK demodulator mixes the BPSK input signal and its copy delayed by a half of the carrier period to generate a data flipping signal whose rising edges indicate when the phases of the BPSK signal flip. The data are then recovered by sampling the BPSK input signal using the derived data flipping signal. A phase selector recovers the coherent clock with a 50% duty cycle by selecting either the delayed BPSK input or its complement according to the recovered data. The open-loop operation of the proposed BPSK demodulator enables it to achieve a data rate as high as the carrier frequency. The all-digital implementation makes the demodulator compact, low power, and able to operate at 0.5 V. A test chip running with a 13.56-MHz carrier has been designed and fabricated. Measurement results show that at 0.9 V and a data rate of 13.56 Mb/s, the proposed demodulator only consumes 12.2 $\mu \text{W}$ , corresponding to an FoM of 0.90 pJ/b. This FoM is at least 61 times better than those of the state-of-the-art designs.

This paper presents a CMOS-MEMS capacitive pressure sensor with differential sensing electrodes integrated with a low-power readout circuit in a single chip. The differential sensing electrodes are designed in the back-end-of-line (BEOL) metal and oxide stacks in a commercial $0.18\mu \mathrm{m}$ 1P6M CMOS process. Compared with other pressure sensors with single sensing elements in the literature, the proposed differential sensing design offers the advantages of sensitivity enhancement and noise reduction. The readout circuit is a low power RC oscillator integrated with the sensor on the same chip to reduce noise and power consumption. The sensor was tested in the range of 50-300 kPa. The measurement results show the proposed sensing capacitors have a pressure sensitivity of 0.72 fF/kPa, the frequency of the readout oscillator has a sensitivity of 0.032%/kPa.

This paper proposes an on-wafer test circuitry for rapidly and accurately characterizing the devices under tests (DUTs) of the DUT array in the wafer acceptance test (WAT) to qualify wafers faster and more reliably. The proposed test cell simply comprises a DUT and a selection MOSFET operating in the saturation region as a current buffer when being activated. An analog feedback loop with a replica-biasing circuit tracks the selected DUT’s output current and automatically biases the selection MOSFET’s gate so as to accurately duplicate the desired setup voltage at the selected DUT’s output node. Comparing with conventional designs using the Kelvin sensing scheme to address the switches’ IR drops, the proposed design has less transistor counts, shorter test time, and no risk of forward-bias p-n junctions. Consequently, it achieves a lower test cost and a higher test throughput. The whole proposed test circuitry including 1024 NMOS DUTs has been designed and fabricated in 90-nm CMOS. The active area is only $60~\mu \text{m}$ by $800~\mu \text{m}$ which is small enough to be placed into the scribe line on wafers as conventional WAT circuitry is. Measurement results demonstrate the proposed design’s efficiency and capability of revealing local process variations.

This paper presents the design, fabrication, and characterization of an inductive complementary metal oxide semiconductor micro-electromechanical systems (CMOS-MEMS) accelerometer with on-chip digital output based on LC oscillators. While most MEMS accelerometers employ capacitive detection schemes, the proposed inductive detection scheme is less susceptible to the stress-induced structural curling and deformation that are commonly seen in CMOS-MEMS devices. Oscillator-based frequency readout does not need analog to digital conversion and thus can simplify the overall system design. In this paper, a high-Q CMOS inductor was connected in series with the low-Q MEMS sensing inductor to improve its quality factor. Measurement results showed the proposed device had an offset frequency of 85.5 MHz, sensitivity of 41.6 kHz/g, noise floor of 8.2 mg/&radic, Hz, bias instability of 0.94 kHz (11 ppm) at an average time of 2.16 s, and nonlinearity of 1.5% full-scale.

This paper presents a gauge pressure sensor based on the standard industrial flexible PCB (FPCB) technology. The wireless LC-resonant sensor consists of a variable sensing capacitor and a planar inductor coil fabricated in FPCB. The air gap of the sensing capacitor is extended through a pressure channel embedded in the FPCB strip to enable relative pressure measurement. Thus, the intracranial pressure (ICP) with respect to local atmosphere can be measured without other calibration means. The flat FPCB structure also facilitates the subdural implantation procedures. Experimental results showed that the proposed gauge pressure sensors with such open sensing structures had much higher frequency sensitivity (0.29%/mmHg) compared with sensors with sealed sensing cavities (0.005%/mmHg) and achieved a resolution of 0.51 mmHg.

This paper proposes a digital background calibration scheme for calibrating the linear and the third-order nonlinear gain errors of the residue amplifiers (RAs) in pipelined ADCs. It is based on a novel multiple-correlation estimation (MCE) technique. We define two correction parameters relating to the gain errors of the RA under calibration. By alternately injecting two bi-level pseudo-random signals with designated amplitudes to the RA through the sub-DAC, the desired correction parameters are estimated according to the correlations of the backend ADC's outputs and the injected pseudo-random signals. Two least-mean-square (LMS) loops are adopted to find and to track the optimal values of the correction parameters. Simulation results of a 12-bit pipelined ADC show that the SNDR is improved from 46.4 dB to 73.4 dB with the help of the proposed calibration design. The proposed calibration scheme has the advantages of simple implementation, no restriction on the input signal of the ADC, fast settling, and running in background.

This paper demonstrates a fully integrated built- in self-test (BIST) �� analog-to-digital converter (ADC) based on the proposed in-phase and quadrature waves fitting (IQWF) procedure. The IQWF procedure enables accurately measuring the phases and amplitudes of test responses so as to enhance the test accuracy of the BIST circuitry. The all-digital BIST circuitry, with on-chip stimulus generator and response ana- lyzer, conducts single-tone functional tests to test for the ADCs characterization results such as signal-to-noise-and-distortion ratio (SNDR), dynamic range (DR), frequency response, input- referred offset, and gain error. Since the IQWF procedure is performed successively in real time, the BIST circuitry does not need huge memory to store all the output samples like conventional fast Fourier transform (FFT) analysis does. The overall hardware overhead only consists of 16.6 k digital gates. The fully integrated BIST �� ADC has been fabricated in 0.18-μm CMOS. Measurement results show that the BIST circuitry reports a peak SNDR of 88. 0d B and aD R of 92. 6d B while the corresponding FFT-based analog tests result in 88. 8a nd 94.1 dB, respectively. Particularly, the BIST circuitry achieves a test bandwidth as wide as the ADCs 20-kHz rated bandwidth, which is the widest to the best of our knowledge. The proposed BIST ADC can be tested without costly external test resources and is thus well suited for the applications in which conventional test resources are not available such as 3-D ICs.

3D-IC is a solution to achieve lower cost and higher performance as the transistor density doubles every 18 months following Moore's law. In recent years, Integrated Fan-Out Wafer-Level Chip-Scale Packaging (InFO WLCSP) is one of the most promising packaging technologies for 3D-IC. In InFO WLCSP, there are some inter-die interconnects. We cannot access these interconnects directly. Therefore, it causes 1-2% test coverage loss. As a result, a built-in self-test (BIST) or other design-for-test (DFT) methodology is necessary to test these interconnects. It is easy to detect open defects and short defects leading to large leakage currents with conventional test methods. However, defects leading to small leakage currents are hard to detect, so we focus on these defects in this work. In this paper, we propose a scheme to measure the small leakage current of these inter-die interconnects. The scheme uses IEEE 1149.1 boundary scan interface. Because boundary scan is a well-adopted standard, the scheme can be integrated into any electronic product easily. Beside four mandatory terminals, we add a reference current input. Users can apply current to compare it with the leakage current. For the input EBSC, two OR gates, a MUX, and a current digitizer are added and it is compared with the conventional BSC. A test chip is implemented to verify our design, which uses the one-polynine-metal (1P9M) 90nm CMOS technology. Measurement results show that the proposed scheme is able to measure the leakage current of the interconnect. In addition, with the dynamic range of 128nA, the current digitizer has 6-bit resolution.

This paper reports a three-axis CMOS MEMS inductive accelerometer fabricated by a 0.18 μm CMOS process. The folded suspension beams around the single shuttle mass function as springs and inductor windings simultaneously. The winding inductance is changed upon deformation due to the shuttle mass displacement. The inductance variation is sensed by differential LC-tank oscillators. A novel z-axis inductive sensing scheme is proposed. Experiments showed sensitivities of 12.9, 21.6, and 1.2 kHz/g in the x, y, and z axes, respectively.

Advanced technology suffers from more severe local process variation and thus requires measuring sufficient process control monitoring (PCM) devices to provide reliable wafer acceptance test (WAT) results. Adopting a large-scale device array with multiplexers can measure more PCM samples at a probe without increasing the pad count. Integrating a high-resolution and robust analog-to-digital converter (ADC) with the PCM circuits to replace the high-end ATE further reduces the test cost. It also alleviates the parasitic effects and thus accelerates the test and enhance the measurement accuracy. However, the on-wafer ADC design for WAT needs to be placed within the scribe line of the wafer. This work proposes a 12-bit dual-slope ADC that meets all the requirements for the aforementioned WAT scenario. The proposed switched-capacitor implementation makes the ADC robust against PVT variations. A test chip has been designed and fabricated in 0.18um CMOS. The active area of the proposed ADC is only 57 um by 581 um which well fits the narrow scribe line. Measurement results show the DNL and INL values are within +1.04/−0.8 and +1.83/−1.72 LSB, respectively. The ADC totally consumes 4.6 mW when operates at 3.3V and 3.2 kS/s.

This paper presents the design and test of a 14 GSps, four-bit data converter pair in 90 nm CMOS suitable for implementing advanced serial links. The data converter pair consists of a noninterleaved flash analog-to-digital converter (ADC) and a noninterleaved current-steering digital-to-analog converter (DAC). Both the converter designs adopt the wave-pipelining technique to increase the available signal settling time. Through detailed analysis, we show that cascading three active feedback preamplifiers to implement the cores of the comparators in the ADC balances the power budget and the design difficulty when we push the sampling rate to the process limit. Current mode logic gates are used to alleviate the power bouncing issue. To address the difficulty and high cost of testing the extremely high-speed converters, the design embeds the simple design-for-testability circuits cooperating with the on-chip resources to provide two cost-effective test modes. The first test mode cascades the ADC and DAC so that they can be tested at the rated speed without the need of a very high speed logic analyzer. The second test mode enables the eye diagram tests by shuffling the digital outputs of ADC as the inputs of the DAC instead of adopting conventional linear feedback shift register. The experimental results show that the cascaded ADC and DAC pair achieves a 31.0 dBc spurious-free dynamic range and a 25.9 dB signal-to-noise-and-distortion ratio with a 1.11 GHz, ${-}{\rm 1}~{\rm dBFS}$ stimulus at 14 GSps. The ADC and DAC consume 214 mW and 85 mW from a 1.0-V supply and occupy 0.1575 ${\rm mm}^{2}$ and 0.0636 ${\rm mm}^{2}$ , respectively.

This paper presents a CMOS-MEMS accelerometer based on differential LC-tank oscillators. Two LC-tank oscillators composed of differential MEMS capacitors and suspended inductors were designed and fabricated by standard TSMC 0.18 μm CMOS processes and post-CMOS dry etching. The outputs of the differential oscillators are mixed and the output frequency of the mixer is proportional to the capacitance change caused by the external acceleration. The device has been characterized and has a mechanical resonance frequency of 7 kHz, absolute sensitivity of 3.62 MHz/g, relative sensitivity of 1.9×10-3 Δf/f0/g, in-axis nonlinearity of 1.2%FS, bias stability of 2.1 mg, and average noise floor of 0.205-0.219 mg/√Hz in the frequency range of 15-250 Hz.

This work presents a fifth-order OTA-C band-pass filter applying Elliptic low-pass filter and complex filter techniques. The frequency error of the filter due to the effect of process variations is induced by integrating the passive components with the operational transconductance amplifier on chip. A filter circuit with automatic calibration scheme can make the frequency less dependent on process, voltage, and temperature variations. The layout of a test chip is realized using a 0.18 um 1P6M CMOS process. Post-layout simulation demonstrates that the center frequency of the band pass filter is 450 kHz and the dynamic range is 35 dB, It has a total power consumption of 0.14mW.

This work presents a low-voltage indoor energy harvesting using photovoltaic cell. The system doesn't use a dc-dc converter to boost the output voltage so that large external inductors and large capacitors are eliminated. A rechargeable battery is connected to the output for storing the energy. No other external components are needed in the system. A test chip is implemented using a 0.18um CMOS process with a chip area of 0.85×0.85mm2 and a power consumption of 272uW. This solar cell provides a voltage of 0.4V∼0.55V to the test chip at a minimum illumination of 61∼625 Lux. A maximum efficiency of 54% can be obtained when the supply voltage is 0.5 V.

High pin count packaging and 3D IC technology make testing such advanced ICs more and more difficult and expensive. The HOY wireless test platform provides an alternative and cost-effective test solution to address the poor accessibility and high test cost issues. The key idea is implementing a low-cost and short-distance wireless transceiver on chip so that all test instructions and data can be transmitted without physical access. Due to the limited wireless bandwidth, all modules in the device under test (DUT) are preferred to have some built-in self-test (BIST) features. Prior works successfully demonstrated that DUTs with memory and digital circuits can be tested on the low-cost wireless test platform. However, there is no example to show if it is also possible to test the DUT embedded with analog circuits on the HOY test platform. This paper demonstrates the first system-level integration including hardware and software for testing a fully-integrated BIST ADC on the HOY wireless test platform. The DUT chip fabricated in 0.18-μm CMOS consists of a second-order Σ–Δ ADC under test (AUT) and the BIST circuitry. The AUT design employs the decorrelating design-for-digital-testability (D3T) scheme to make itself digitally testable. The BIST design is based on the modified controlled sine wave fitting (CSWF) method. The required BIST circuits are purely digital and as small as 9.9k gates. The gate count of the HOY test wrapper is less than 1k. Experimental results obtained by the HOY wireless test platform show that the AUT achieves a dynamic range of 85.1 dB and a peak SNDR of 78.6 dB. The wireless test results show good agreement with those acquired by conventional analog tests.

This paper proposes a static linear behavior (SLB) analog fault model for switched-capacitor (SC) circuits. The SC circuits under test (CUT) are divided into functional macros including the operational amplifiers, the capacitors, and the switches. Each macro has specified design parameters from the design's perspectives. These design parameters constitute a parameter set which determines the practical transfer function of the CUT. The SLB fault model defines that a CUT is faulty if its parameter set results in transfer functions whose frequency responses are out of the design specification. We analyzed the fault effects of the macros and derived their faulty signal-flow graph models with which the faulty transfer function templates of the CUT can be automatically generated. Based on the templates, we proposed a test procedure that can estimate all the parameters in the parameter set so as to test the CUT with multiple faults. Different from conventional single fault assumption, the proposed SLB fault model covers concurrent multiple parametric faults and catastrophic faults. In addition, it does not need to conduct fault simulations before test as conventional analog fault models do. As a result, it addresses the impractically long fault simulation time issue. A fully-differential low-pass SC biquad filter was adopted as an example to demonstrate how to design and use efficient multitone tests to test for the parameter set. The multitone test results acquired during the test procedure also reveal the distortion and noise performance of the CUT though the SLB fault model does not include them.

This paper demonstrates a digitally testable second-order Σ - Δ modulator. The modulator under test (MUT) employs the decorrelating design-for-digital-testability (D3T) scheme to provide two operation modes: the normal mode and the digital test mode. In the digital test mode, the input switched-capacitor network of the D3T modulator is reconfigured as two sub-digital-to-charge converters (sub-DCCs). Each of the sub-DCCs accepts a Σ - Δ modulated bit-stream as its test stimulus. By repetitively inputting the DCCs with the same Σ - Δ modulated bit-stream but with different delays, the DCCs incorporates with the integrator to generate the analog stimulus in the digital test mode. The analog stimulus is analogous to the result of filtering the bit-stream with a two-nonzero-term FIR decorrelating term. Consequently, the D3T MUT suffers less from the undesired shaped noise of the digital stimuli, and achieves better digital test accuracy. Measurement results show that the digital tests present a peak signal-to-noise-and-distortion ratio (SNDR) of 80.1 dB at an oversampling ratio of 128. The SNDR results of the digital tests differ from their conventional analog counterparts by no more than 2 dB except for the -3.2 dBFS test. The analog hardware overhead of the D3T MUT only consists of 13 switches.

This paper demonstrates the first fully integrated built-in self-test (BIST) Σ-Δ analog-to-digital converter (ADC) chip to the best of our knowledge. The ADC under test (AUT) comprises a second-order design-for-digital-testability Σ-Δ modulator and a decimation filter. The purely digital BIST circuitry conducts single-tone tests for the signal-to-noise-and-distortion ratio (SNDR), the dynamic range, the offset, and the gain error of the AUT. The BIST design is based on the proposed modified controlled sine-wave fitting procedure to address the component overload issues, reduce the setup parameter numbers, and eliminate the need for parallel multipliers. The total gate count of the whole BIST circuitry is only 13 300. The hardware overhead is much less than the BIST design using the traditional fast Fourier transform (FFT) analysis. Measurement results show that the peak SNDR results of the proposed BIST design and the conventional FFT analysis are 75.5 and 75.3 dB, respectively. The subtle SNDR difference is already within analog test uncertainty. The BIST Σ-Δ ADC achieves a digital test bandwidth higher than 17 kHz, very close to the rated 20-kHz bandwidth of the AUT.

This paper presents a built-in-self-test (BIST) Σ-Δ ADC prototype. The BIST circuity uses the proposed modified controlled sine wave fitting (CSWF) procedure to calculate the signal power and the total-harmonic-distortion-and-noise power in time domain separately. Compared with conventional Fast Fourier Transform (FFT) analysis, neither complex CPU/DSP nor bulky memory is required. The added BIST circuitry is purely digital and the hardware overhead is as low as 11.9 K gates. A prototype comprising the second-order design-for-digital-testability Σ-Δ modulator chip and an FPGA board which implements the digital functions is used to demonstrate the effectiveness of the BIST design. Measurement results show that the SNDR difference between conventional FFT analysis and the proposed BIST design of the standard − 6 dBFS, 1 KHz tone test is only 0.3 dB. Furthermore, the tested dynamic range values by both methods are the same. The proposed BIST implementation achieves the advantages of compact hardware, high test accuracy, and the flexibility of adjusting the stimuli which are important features for BIST applications.

This paper presents a novel decorrelating design-for-digital-testability (D3T) scheme for Sigma-Delta modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order Sigma-Delta modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than -5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the D3T scheme has the potential to test moderate nonlinearity. The proposed D3T scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.

A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Sigma-Delta modulators with digital stimuli is presented to reduce the overall testing cost. In the test mode, the DfDT circuits are reconfigured as a one-bit digital-to-charge converter to accept a repetitively applied Sigma-Delta modulated bit-stream as its stimulus. The single-bit characteristic ensures that the generated stimulus is nonlinearity free. In addition, the proposed DfDT structure reuses most of the analog components in the test mode and keeps the same loads for the operational amplifiers as if they were in the normal mode. It thereby achieves many advantages including lower cost, higher fault coverage, higher measurement accuracy, and the capability of performing at-speed tests. A second-order Sigma-Delta modulator was designed and fabricated to demonstrate the effectiveness of the DfDT structure. Our experimental results show that the digital test is able to measure a harmonic distortion lower than -106 dBFS. Meanwhile, the dynamic range measured with the digital stimulus is as high as 84.4 dB at an over-sampling ratio of 128. The proposed DfDT scheme can be easily applied to other types of Sigma-Delta modulators, making them also digitally testable.

Evaluating the digital stimuli used in the design-for-digital-testability (DfDT) Σ-Δ modulator is a time-consuming task due to its oversampling and non-linear nature. Although behavioral simulations can substantially improve the simulation speed, conventional behavioral models fail to provide accurate enough signal-to-noise ratio (SNR) predictions for this particular application. In this paper, a fully-settled linear behavior plus noise (FSLB+N) model for the DfDT Σ-Δ modulator is presented to improve both the accuracy and the speed of the behavioral simulations. The model includes the following parameters: the finite open-loop gains, the offsets, the finite output swings, the flicker noise of the operational amplifiers (OPAMPs), as well as the thermal noises of the switched capacitors, the OPAMPs, and the reference supplies. With the proposed model, the behavioral simulation results demonstrate a high correlation with the measurement data. On average, the SNR difference between the simulation and the measurement is ---1.1 dB with a maximum of 0.05 dB and a minimum of ---2.2 dB. Comparing with the circuit-level simulation using HSPICE, the behavioral simulation with the FSLB+N model is 1,190,000 times faster. The proposed model not only can be used for evaluating the digital stimulus candidates, but also can be applied to system-level simulations of the mixed-signal design with an embedded DfDT Σ-Δ modulator.

An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 mum CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 muW in the test, corresponding to a figure of merit of 65 f J/conversion-step.