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Microlens array (MLA) is microfabricated using Ultra Violet (UV) laser for display device applications. A colorless liquid photopolymer, Norland Optical Adhesive (NOA) 60, is spin-coated and pre-cured via UV light for completing the laser process. The laser energy controlled by a galvano scanner is radiated on the surface of the NOA 60. A rapid thermal volume expansion inside the material creates microlens array when the Gaussian laser energy is absorbed. The fabrication process conditions for various shapes and densities of MLA using a non-contact surface profiler are investigated. Furthermore, we analyze the optical and display characteristics for the Organic Light Emitting Diode (OLED) devices. Optimized condition furnishes the OLED with the enhancement of light emission by 15%. We show that UV laser technique, which is installed with NOA 60 MLA layer, is eligible for improving the performance of the next generation display devices.

Vertical diodes for cross-point phase change memory were realized by selective epitaxial growth (SEG) technique using cyclic chemical vapor deposition method. H2/SiH4/Cl2 cyclic CVD system was introduced in batch-type vertical furnace equipement, replacing conventional single-wafer H2/dichlorosilane/HCl CVD system. It provided excellent capacity of 40 wafers per batch. Selectivity loss which is one of the most crucial features in SEG process for diode application was controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and practical value of selectivity loss was confirmed to be less than 100 in 200-mm wafers. Structural and electrical properties of pn diodes were investigated, and cyclic SEG silicon diode showed more eligible electrical ability to current flow than that of poly-si in terms of forward current and ideality factor as well as lower reverse leakage current.

In this letter, a cost-effective vertical diode scheme for next-generation memory devices, including phase-change memories (PCMs), is realized. After the contact formation for diodes with only one mask layer, an amorphous silicon (a-Si) film was deposited within the contacts using SiH4 ramp-up ambient in a conventional batch-type furnace in order to minimize the growth of native oxide. A deposition/etch-back/deposition scheme enabled us to achieve robust vertical diodes without any seams or interfacial oxide layer within the vertical diode pillars. Subsequent annealing at 600 °C provided solid-phase epitaxial alignment of the a-Si layer. An ideality factor revealed that the new scheme provided noticeable crystallinity of the silicon diodes. Moreover, the electrical characteristics of the diodes verified that the scheme was suitable for full operation of PCM devices.

The doping profiles of lightly doped semiconductors are most commonly determined from capacitance-voltage measurements for junction devices. Such C-V measurements work well for large-area devices and lightly doped device, but they are not very suitable for high doping concentrations found in heavily doped devices (1). And the channel region under the MOSFET gate has an additional limitation. The small gate area has very small capacitances that are difficult to measure, making C-V based techniques difficult or impossible. In view of these experimental difficulties, so we tried electrical doping profiling measurement for MOSFET with short gate length and ultra thin oxide thickness and checked an agreement with ISE simulation results.

Practical selectivity window of selective epitaxial growth (SEG) using a H2/SiH4/Cl2 cyclic chemical vapor deposition (CVD) system has been investigated with the batch-type vertical furnace equipment, replacing a conventional single-wafer H2/dichlorosilane/HCl CVD system. The process temperature was less than 700 °C, which is suitable for a low thermal budget process applicable to next-generation memories including vertical pn-diode switches. Selectivity loss is quantified by an in-line inspection tool to determine the practical number of selectivity losses. The H2/SiH4/Cl2 cyclic CVD system provides an excellent capacity of 40 wafers per batch. Selectivity loss, which is one of the most crucial features in the SEG process for the diode application, is controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and the practical number of selectivity loss is confirmed to be less than 100 in 200 mm wafers. Without high temperature annealing in hydrogen ambient, low temperature cyclic SEG in the batch reactor ensures the clean interface and improved crystalline quality of SEG-Si, as well as high throughput.

Solid phase epitaxy (SPE) techniques have been studied to realize stacked static random memory (SRAM) devices. Among the candidates including epitaxial lateral overgrowth (ELO) and laser epitaxial growth (LEG) techniques, SPE is the most stable and cost-effective scheme since it is fulfilled by the deposition of amorphous silicon layers and the subsequent low temperature annealing using conventional furnace equipment which has been used for several decades in semiconductor fabrication. We introduced silicon seeds for the epitaxial realignment of amorphous silicon within the contact window by the selective epitaxial growth (SEG) of single-crystalline silicon. The role of process variables associated with channel silicon deposition on SPE was investigated. The efficiency of SPE was quantified by electron back-scatter diffraction (EBSD) measurement, which visualizes the fraction of the orientation in a channel silicon layer. SiH4 ambient during the ramp-up stage in the deposition of amorphous silicon layers showed superior epitaxial realignment to N2 ambient, which was mainly due to the suppression of interfacial layer formation. Electrical characteristics such as on-current distribution and static noise margin indicated SPE to be feasible for high-density stacked SRAM application.

Selectivity control in silicon selective epitaxial growth (SEG) for deep contact patterns, which is one of the key processes for silicon-based stacked devices and cell switches for next generation memories, was studied. Absolute values of selectivity loss during silicon SEG using the most popular H2/dichlorosilane (DCS)/HCl gas system were evaluated using a commercialized inspection tool in 200 mm wafers with real contact patterns. It was revealed that HCl/(DCS+HCl) ratio and the contact structure played a crucial role in suppressing selectivity loss. The number of selectivity losses in an entire wafer was less than 100 when the HCl/(DCS+HCl) ratio was larger than 0.41. The vertical pn diode prepared using the silicon SEG process with elaborate selectivity control showed more remarkable electrical abilities to accommodate current flow than polycrystalline silicon (poly-Si), including the ideality factor and swing, and reverse leakage current.

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