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International audience; SETs (Single-Electron-Transistors) arouse growing interest for their very low energy consumption. For future industrialization, it is crucial to show a CMOS-compatible fabrication of SETs, and a key prerequisite is the patterning of sub-20 nm Si Nano-Pillars (NP) with an embedded thin SiO2 layer. In this work, we report the patterning of such multi-layer isolated NP with e-beam lithography combined with a Reactive Ion Etching (RIE) process. The Critical Dimension (CD) uniformity and the robustness of the Process of Reference are evaluated. Characterization methods, either by CD-SEM for the CD, or by TEM cross-section for the NP profile, are compared and discussed.

For future nanoelectronic devices - such as room-temperature single electron transistors - the site-controlled formation of single Si nanocrystals (NCs) is a crucial prerequisite. Here, we report an approach to fabricate single Si NCs via medium-energy Si+ or Ne+ ion beam mixing of Si into a buried SiO2 layer followed by thermally activated phase separation. Binary collision approximation and kinetic Monte Carlo methods are conducted to gain atomistic insight into the influence of relevant experimental parameters on the Si NC formation process. Energy-filtered transmission electron microscopy is performed to obtain quantitative values on the Si NC size and distribution in dependence of the layer stack geometry, ion fluence and thermal budget. Employing a focused Ne+ beam from a helium ion microscope, we demonstrate site-controlled self-assembly of single Si NCs. Line irradiation with a fluence of 3000 Ne+/nm2 and a line width of 4 nm leads to the formation of a chain of Si NCs, and a single NC with 2.2 nm diameter is subsequently isolated and visualized in a few nanometer thin lamella prepared by a focused ion beam (FIB). The Si NC is centered between the SiO2 layers and perpendicular to the incident Ne+ beam., Comment: 10 pages, 6 figures

With the transition to ≤28-nm CMOS technology nodes, the surface analytical challenges with regard to steadily decreasing dimensions and still growing materials options raise the demand of high performing surface analysis techniques. Characterization of ultrathin films and multilayer stacks, especially in high-k metal gate stacks, by means of low energy ion scattering spectroscopy (LEIS) with its monolayer sensitivity has been established as a very useful analysis technique next to Auger electron spectroscopy, X-ray photoelectron spectroscopy, and time-of-flight secondary ion mass spectrometry. Questions regarding film nucleation, growth, coverage, and diffusion can be answered, thereby enabling those processes to be controlled appropriately. In this work, growth studies of ALD HfO2 and TiN are shown, as well as film thickness determination based on surface spectra. PVD aluminum and lanthanum, acting as work function metals on the gate oxide, were deposited, and their film formation and closure were investigated. Further application fields of LEIS have emerged from the characterization of in-die features on patterned wafers. As presented on test arrays, it is possible to detect material deep in trenches. This is an advantage if residues need to be identified after etch or clean processes.

A single sheet of Si nanoclusters with an average diameter of about 2 nm has been formed in a 30 nm Si/7 nm SiO2/Si layer stack by 50 and 60 keV Si+ ion-beam mixing at room temperature and fluences between 8.5 ⋅ 1015 and 2.6 ⋅ 1016 ions/cm2 and by subsequent thermal annealing at a temperature above 1000 °C. Computer modeling of the process is accomplished by TRIDYN dynamic ballistic simulation of ion mixing and subsequent lattice kinetic Monte Carlo simulation of the phase decomposition of substoichiometric silicon oxide into Si nanoclusters in a SiO2 matrix. The simulation algorithms are briefly described with special emphasis on the choice of governing parameters for the present system. In comparison to the experimental results, it is concluded that the predicted ion mixing profiles overestimate the interface broadening. This discrepancy is attributed to the neglect of chemical driving forces in connection with thermal-spike induced diffusion, which tends to reconstitute the Si/SiO2 interfaces. With a corresponding correction and a suitable number of Monte Carlo steps, the experimentally obtained areal densities and average diameters of the nanoclusters are successfully reproduced.A single sheet of Si nanoclusters with an average diameter of about 2 nm has been formed in a 30 nm Si/7 nm SiO2/Si layer stack by 50 and 60 keV Si+ ion-beam mixing at room temperature and fluences between 8.5 ⋅ 1015 and 2.6 ⋅ 1016 ions/cm2 and by subsequent thermal annealing at a temperature above 1000 °C. Computer modeling of the process is accomplished by TRIDYN dynamic ballistic simulation of ion mixing and subsequent lattice kinetic Monte Carlo simulation of the phase decomposition of substoichiometric silicon oxide into Si nanoclusters in a SiO2 matrix. The simulation algorithms are briefly described with special emphasis on the choice of governing parameters for the present system. In comparison to the experimental results, it is concluded that the predicted ion mixing profiles overestimate the interface broadening. This discrepancy is attributed to the neglect of chemical driving forces in connection with thermal-spike induced diffusion, which tends to reconstitute the Si/SiO2 interfaces. With a c...

Si nanopillars of less than 50 nm diameter have been irradiated in a helium ion microscope with a focused Ne+ beam. The morphological changes due to ion beam irradiation at room temperature and elevated temperatures have been studied with the transmission electron microscope. We found that the shape changes of the nanopillars depend on irradiation-induced amorphization and thermally driven dynamic annealing. While at room temperature, the nanopillars evolve to a conical shape due to ion-induced plastic deformation and viscous flow of amorphized Si, simultaneous dynamic annealing during the irradiation at elevated temperatures prevents amorphization which is necessary for the viscous flow. Above the critical temperature of ion-induced amorphization, a steady decrease of the diameter was observed as a result of the dominating forward sputtering process through the nanopillar sidewalls. Under these conditions the nanopillars can be thinned down to a diameter of ∼10 nm in a well-controlled manner. A deeper understanding of the pillar thinning process has been achieved by a comparison of experimental results with 3D computer simulations based on the binary collision approximation.

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The time dependent dielectric breakdown (TDDB) in copper/ultra-low-k on-chip interconnect stacks of integrated circuits has become one of the most critical reliability concerns in recent years. In this paper, a novel experimental in situ microscopy approach using transmission X-ray microscopy (TXM) and scanning transmission electron microscopy (STEM) is proposed to study TDDB degradation and failure mechanisms. It combines electrical testing and imaging techniques. Low-dose bright field (BF) STEM inserting a small condenser aperture is chosen to reduce the beam damage of the dielectric material, while the electron spectroscopic imaging technique is used for the chemical analysis to detect the migration path of Cu atoms. This new experimental approach will contribute to an improved understanding of the TDDB effect.

We introduce a method to characterize the chemical distribution in nanostructures using STEM and affiliated spectroscopy techniques. The method is applicable to any nanostructure where the continuous layers of arbitrary geometry and dimensions can be identified. The key feature of the suggested approach is digital warping of the original STEM image into the quasi-1D image. The chemical profiles of high resolution and high signal-to-noise ratio can be extracted from the minimal set of the STEM spectroscopy data while minimizing material damage during acquisitions. Finally, the 2D chemical maps of the area of interest are reconstructed.

A major challenge for the application of strain engineering to enhance the performance of electronic devices is the quantification of strain on the nanoscale. Besides other techniques (Raman spectroscopy, X-ray diffraction) electron beam techniques allow strain analyses with a spatial resolution of a few nanometers and a reasonable strain sensitivity of 1x10 -3 (relative to the lattice constant of silicon). In the present work, we address practical issues in the application of nano-beam electron diffraction (NBED) to probe the strain in strained silicon layers and sub-100 nm structures. The investigated specimens were prepared on biaxially tensile strained silicon-on- insulator substrates with an initial strain of = 0.6% or 0.8%. Results of the NBED experiments were compared to data obtained by other strain measurement techniques; amongst them the strain mapping by peak-pairs analysis of high-angle annular dark field (HAADF) images was especially considered. NBED can be easily performed by use of STEM with a small aperture of the 2 nd condenser lens in the micro- or nanoprobe mode. The NBED principle consists in illuminating a nanometer-sized area of the specimen (being in zone axis orientation) with a nearly parallel electron beam and acquiring series of diffraction patterns at points along previously defined lines. The strain components of interest are generally calculated using a dedicated software package which is based on procedures for the analysis of electron diffraction patterns. The spatial resolution of NBED is determined by the beam diameter to a few nanometers. The

Interface formation between 25-m AlSi1 wire and flash-Au substrate metallization during a bonding time of 50 ms has been investigated. Only a few milliseconds after the ultrasonic power is switched on, intermetallic phase growth starts, continuing until the end of the wire-bonding process. During the entire bonding time, the fraction of the interface covered with Au 8Al3 increases, and at the end of the bonding time, the interface is nearly completely covered with that phase. Finite-element modeling (FEM) of the temperature in the interface region indicates maximum temperatures well below 100°C, thus making solely thermally activated intermetallic phase growth impossible. However, it is demonstrated that the phase growth observed during the ultrasonic wire-bonding process could result from an accelerated diffusion process caused by a higher vacancy concentration. The accelerated diffusion process would have an activation energy Q of 0.36 eV.

Energy-dispersive X-ray spectrometry (EDXS) in the transmission electron microscope (TEM) is applied for accurate spatially resolved quantitative chemical analysis of SiGe structures implemented into high-performance complementary metal oxide semiconductor (CMOS) transistors. For fast and high-quality TEM target specimen preparation, an advanced focused ion beam (FIB)-based lift-out technique employing Be half ring grids is developed to significantly minimize post-specimen scatter artifacts during EDXS data recording. Based on systematic variation of acquisition parameters (dwell time, sampling area) at fixed beam current, the influence of electron irradiation on microstructure and composition of SiGe alloys is studied, and a critical electron fluence for beam-induced damage is identified. While chemical analysis is unaffected for smaller values, higher electron fluences cause atom displacement by surface sputtering. Applying optimal acquisition parameters for accurate composition analysis at standard TEM settings, spatially confined graded embedded SiGe cavities, introduced into the CMOS process flow to transfer compressive stress into the pMOS transistor channel, are characterized.

Valence EELS combined with STEM provides an approach to determine the dielectric constant of materials in the optical range of frequencies. The paper describes the experimental procedure and discusses the critical aspects of valence electron energy-loss spectroscopy (VEELS) treatment. In particular, the relativistic losses might affect strongly the results, and therefore they have to be subtracted from the spectra prior the analysis. The normalization of the energy-loss function is performed assuming an uniform thickness of the investigated area, which is reasonably fulfilled for carefully prepared FIB samples. This procedure requires the presence of at least one reference material with known dielectric properties to determine the absolute thickness. Examples of measuring the dielectric constant for several materials and structures are presented.

Investigation of stress migration phenomena is one of the key aspects to characterize metallization reliability. Typical test methodologies are investigations of resistance shifts at wafer-level or package-level temperature storage tests under a temperature range between 150^oC and 275^oC. During these tests a very limited resistance increase dependent on the test structure is allowed. Most recently we encounter unusual resistance shift at the highest stress temperature which did not yield classical stress voiding detectable by failure analysis. We found changes in barrier integrity explaining the resistance shift by barrier oxidization. This has been verified by specially prepared material as well as extensive failure analysis investigation.

Display Omitted We studied the TDDB-induced damage mechanism in Cu/ULK structures in-situ.The methodology combined TEM imaging, ESI analysis and in-situ electrical testing.Three major TDDB-induced damage mechanisms were observed.The breakdown spot depends on the materials, geometry and the degradation effects.The results highlight the importance of the quality of the deposition process for the Ta-based barrier. The time-dependent dielectric breakdown (TDDB) mechanism in Cu/ultra-low-k (ULK) on-chip interconnect structures has been raising serious reliability concerns for state-of-the-art microelectronic devices in recent years. An advanced experimental methodology, which combines transmission electron microscopy (TEM) imaging and an in-situ electrical test using a Hysitron PI95 TEM holder, was used to study TDDB-induced damage mechanisms and degradation kinetics in Cu/ULK interconnect structures. In flawless Cu/ULK interconnect structures with locally very thin Ta-based barriers, slow but massive Cu migration into the SiO2 layer was observed at the bottom corner of the M1 metal after the TaN/Ta barrier had been firstly ruptured by the Ta migration, driven by the high electrical field. More importantly, it was found that both the high electric field and the massive metal migration into the SiO2 can contribute to the final breakdown of the Cu/ULK interconnect structures. The final breakdown spot could be located either at the interface of the SiCN layer and the ULK material or in the SiO2 layer, which depends on the geometry, the kind of dielectric materials (particularly ULK) and the driving force (the high electric field). The results also highlight the importance of the quality of TaN/Ta barrier deposition process, especially at the bottom corner of the M1 metal, to ensure the functionality of the TaN/Ta barriers during the product lifetimes.

Electromigration (EM) in sub-micron metal interconnects depends on interface bonding and metal microstructure. The process of EM-induced degradation in on-chip interconnects as observed from both in-situ scanning electron microscopy (SEM) experiments at embedded inlaid copper interconnect structures and numerical simulations based on a physical model is explained based on transmission electron microscopy (TEM) brightfield images. Interface strengthening results in completely changed degradation and failure mechanisms. The changed void evolution for interconnects with strengthened interfaces, e.g. caused by additional metal coating like CoWP or self-assembled monolayers (SAMs) on top of the polished copper lines, is explained with increased atomic order and stronger bonding compared to standard Cu/SiN x interfaces.

The effect of the nitrogen content on the thermal stability and degradation mechanisms of Ta–Si–N diffusion barriers was studied using methods that prove Cu interdiffusion. On the one hand, glancing angle X-ray diffraction was applied to detect Cu 3 Si formation after annealing of Cu/Ta–Si–N/Si layer stacks. On the other hand, a combined secondary ion mass spectroscopy and transmission electron microscopy analysis of Ta–Si–N/Cu/Ta–Si–N/SiO 2 /Si samples was performed. For a detailed investigation of the microstructure evolution, the crystallization behavior of both Cu-capped and uncapped Ta–Si–N/Si samples was analyzed using X-ray diffraction. In the case of an uncapped Ta 73 Si 27 film, Si interdiffusion from the substrate precedes the layer crystallization. The substrate influence on the crystallization process decreases with increasing N content x N of the Ta–Si–N layer. Using Cu/Ta–Si–N/Si samples, a critical temperature for Cu silicide formation was determined. This temperature increases with increasing N content of the Ta–Si–N barrier. In the case of Ta–Si–N films with x N > 25 at.%, Cu interdiffusion into the substrate occurs before a significant barrier crystallization is observed. For Ta–Si–N layers with x N ≤ 25 at.%, no indications for Cu diffusion before crystalline phase formation were detected.

Both in situ microscopy experiments at embedded inlaid copper interconnect structures and numerical simulations based on a physical model provide information about electromigration-induced degradation mechanisms in on-chip interconnects. It is shown that the modification of the bonding strength of the weakest interface results in completely changed degradation and failure mechanisms. Transmission electron microscopy (TEM) images of standard Cu/SiNx interfaces are compared with strengthened interfaces, e. g., after applying an additional metal coating or a self-assembled monolayer (SAM) on top of the polished copper lines. The changed degradation mechanisms as observed with the in situ scanning electron microscopy (SEM) experiment and as predicted based on the numerical simulations are explained based on TEM images.

The thermal stability of a SiNx passivation layer and its influence on the annealing behavior of an amorphous Ta73Si27 diffusion barrier deposited between copper and SiO2 were analyzed by X-ray diffraction, glow discharge optical emission spectroscopy, Auger electron spectroscopy, scanning electron microscopy, and transmission electron microscopy. During heat treatment at a temperature Tan = 500 °C, diffusion of Cu atoms out of the Cu metallization into the SiNx passivation occurs. The Cu diffusion intensifies with increasing annealing temperature and annealing time and seems to be a necessary precondition for a defect formation process observed within the Cu metallization. Depending on the chemical composition of the SiNx/Cu interface, voids in the μm-range can be formed within the Cu film. Compared to an unpassivated sample, heat treatment leads to a reduced diffusion of Ta atoms from the barrier through the copper into the SiNx/Cu interface. The barrier crystallization process into Ta5Si3 occurring during annealing at Tan = 600 °C is principally not affected by the presence of a SiNx passivation. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The influence of N content on the crystallization behavior of initially amorphous Ta–Si–N diffusion barriers deposited with a thickness of 10 nm between Cu and SiO 2 was investigated by means of glancing angle X-ray diffraction (XRD), glow discharge optical emission spectroscopy (GD-OES), transmission electron microscopy (TEM), and graphite furnace atomic absorption spectrometry (GF-AAS) after annealing for various times at a temperature of T an =600 °C. For a Ta 73 Si 27 film, only Ta silicide phases (Ta 5 Si 3 , Ta 2 Si) are formed, whereas all barriers containing nitrogen crystallize primarily into a Ta nitride. Si is not incorporated into this phase but diffuses mostly into the Cu film. Although the crystalline Ta nitride grows mainly within the original barrier region, it does not form a continuous layer. For barriers with a N content x N ≥25 at.%, the annealing time necessary to start the crystallization increases and the formed Ta nitride phases become N-richer (Ta 2 N→Ta 5 N 6 ). A Ta 30 Si 18 N 52 layer maintains its amorphous structure even after annealing for t an =100 h. With increasing N content in the barrier, the thermal stability against Cu diffusion is improved.

The degradation mechanisms of 10 nm thick Ta and Ta 73 Si 27 diffusion barriers deposited between Cu and SiO 2 are compared by means of X-ray reflectometry, glancing angle X-ray diffraction, glow discharge optical emission spectroscopy depth profiling and transmission electron microscopy analysis. Annealing the samples at T an =600 °C for t an =1 h results in a diffusion of Ta atoms through the Cu capping layer to the sample surface, particularly in the case of the pure Ta barrier. During longer heat treatment ( t an >1 h), microstructural changes occur within both barrier types. Whereas the amorphous Ta–Si layer starts to crystallize into Ta 5 Si 3 , the initially grown metastable β-Ta of the pure Ta film transforms into the equilibrium α-Ta phase. Analyzing the diffusion rate of Cu atoms into the substrate, the Ta 73 Si 27 barrier shows an enhanced thermal stability compared to the pure Ta film.

Transmission electron microscopy (TEM) is increasingly used for characterizing structures that are shrunk continuously, especially microelectronic devices. Conventional focused ion beam technique (FIB technique) is used routinely in the semiconductor industry for time-efficient and reliable target preparation of TEM lamellas. The combination of FIB and lift-out technology using needle manipulators represents a new technical solution for sample preparation for 3-dimensional (3D-) TEM. The process steps for this are described in this article, requirements to optimal sample carriers are discussed and the suitability of the procedure is demonstrated by means of TEM images.

Sputter deposited Ta and TaN single layers of 10 nm thickness as well as graded TaN/Ta and Ta/TaN/Ta layer stacks that act as diffusion barriers for Cu metallization were investigated after annealing at temperatures between T an =300 and 700 °C. By means of glancing angle X-ray diffraction, glow discharge optical emission spectroscopy and transmission electron microscopy, results of microstructure and phase characterization were correlated with diffusion phenomena. For the pure Ta barrier, Ta diffusion through the Cu cap layer to the sample surface is observed at T an =500 °C, and the transformation of initially grown metastable β-Ta into the equilibrium α-Ta phase occurs at T an =600 °C. In contrast, a fcc TaN layer remains stable at least up to T an =700 °C. In the case of the graded layer stacks, first signs of N diffusion out of the TaN film into the adjacent Ta layers are observed after annealing at T an =300 °C, and formation of hexagonal Ta 2 N starts at T an =500 °C. Whereas in the course of thermal treatments for the threefold graded Ta/TaN/Ta barrier all TaN reacts with Ta to form Ta 2 N, some fcc TaN remains in the twofold graded TaN/Ta barrier.

TEM sample preparation using FIB has become an interesting alternative to classical TEM preparation. This article discusses the capabilities and limits of the FIB technique which are based on results from reference documents and in-house Investigations. It focuses on the real FIB process because it is the only process which determines the properties of the TEM lamella. This article shows that the FIB technique is a very efficient preparation method which ensures a nearly 100% rate of success even if a target preparation is made. Various problems in preparation which were initially considered to be limiting factors may be eliminated or at least mitigated by steps that can be introduced easily. The article describes the problems which are still unsettled and sets forth possible ways to remedy them.

Defined mechanical and electrical properties can be achieved by alloying of aluminum and a subsequent thermo-mechanical treatment. The transmission electron microscopy is used for the characterization of the precipitations and dispersoides which determine these properties. Selected materials regions require special techniques for the preparation of samples. The TEM sample preparation of such regions using the focused ion beam-technique leads to excellent results in the TEM analysis. This will be illustrated through two examples.

Due to the continuing downscaling of transistor and interconnect structures in microelectronic products, today only transmission electron microscopy (TEM) is capable of on-product analysis of the smallest structures with sufficient spatial resolution. However, finite specimen thickness complicates the interpretation of conventional TEM images. Electron tomographic three-dimensional object reconstruction is a promising approach to overcome this limitation. We applied this technique for the first time to characterize Cu interconnect Ta-barrier/Cu-seed layer stacks deposited under different conditions. Their roughness and step coverage becomes clearly visible in the reconstructions. Current possibilities and limitations of this technique as well as future requirements are discussed.

Microstructure, phase composition and interface properties of 10- and 50-mm thick CVD-deposited W-N layers covered with Cu were investigated. Phase formation and structural changes of the layer stacks occurring at elevated temperatures (450-600 °C) were correlated. The initially amorphous barriers undergo an abrupt crystallization between 550 °C/1 h and 600 °C/1 h anneals in vacuum. Further annealing at 600 °C up to 16 h leads to changes in the layer configuration such as N redistribution and Cu agglomeration. No signs of significant Cu diffusion through the barriers were observed for the performed anneals up to 600 °C/16 h.

Structural properties of thin Ta and Ta–N films acting as diffusion barriers were investigated. Blanket Ta-based films of 10 nm thickness were deposited by conventional sputtering techniques onto (100)-Si and covered with a Cu cap layer. X-ray diffraction, depth profile analysis and electron microscopy were used to correlate results of microstructure and phase characterization with diffusion phenomena. Different barrier failure mechanisms were observed after annealing at temperatures between 450 and 800 °C. Ta and Cu silicides were formed suddenly in layer stacks with pure Ta and Ta–20 at.% N barrier films at 550 °C. The application of the stoichiometric TaN as a diffusion barrier prevents the formation of Ta silicides and does not lead to significant Cu silicide formation up to 800 °C. However, trace Cu diffusion into the substrate was also detected at lower temperatures. The barrier stability against Cu diffusion is improving with increasing N content.

Transmission electron microscopy (TEM) gains increasing importance in characterizing microelectronic components since the characteristic structures become smaller and smaller. Transmission electron microscopic investigations need specially prepared samples. The known conventional preparation techniques require a large amount of time. However, the Focused Ion Beam (FIB) method makes it possible to prepare samples for TEM within a short time and with a high success rate. In this paper, target preparation using the FIB method is described with reference to examples for VLSI components. Possible ways and limits of this preparation method are discussed subsequently.

The ongoing scaling-down of semiconductor device structures requires new techniques for cross-sectional thin film characterization. Energy filtering transmission electron microscopy was used for both elemental mapping and electron energy-loss near edge structure (ELNES) mapping of Si compounds. Si, Si 3 N 4 and SiO 2 layers could be clearly differentiated by elemental mapping as well as by ELNES mapping. A clear differentiation of the two phases in CoSi/CoSi 2 layer stacks was only possible by ELNES mapping. It is shown that specific energy filter settings allows distinction between all the Si compounds using only the Si–L 2,3 electron energy-loss edge and the respective electron energy-loss near edge structures.

Thin film and interface characterization are necessary in semiconductor industry to ensure high yields and the required reliability of the products. Particularly, the analysis of layer stacks is a challenging task. Transmission electron microscopy (TEM) essentially contributes to layer stack analysis in microelectronic products. Capabilities and limits of analytical TEM techniques as well as advanced TEM sample preparation techniques are discussed for front-end (MOS transistor) and back-end (interconnect) structures. Typical examples for advanced microprocessor devices are shown.

TEM imaging combined with electron diffraction and analytical methods like EDS and EELS becomes increasingly important in cross-sectional on-product characterization and failure analysis in semiconductor industry, mainly driven by the ongoing scaling-down of device structures. A new analytical technique - energy filtering transmission electron microscopy (EFTEM) - is used more and more in physical failure analysis. Improved TEM sample preparation techniques like the FIB-cut technique allow the reliable target preparation of defects even in the case that a defect has already been prepared for SEM analysis. The application of analytical TEM for failure analysis is demonstrated for particle issues, open electrical contacts in tungsten LI and degradation of AlCul interconnects.

Chemical bonds in [email protected] dielectric materials can be studied at nanometer spatial resolution using electron energy loss spectroscopy (EELS) in a monochromated transmission electron microscope (TEM). However, it is unknown to what extent TEM sample preparation and exposure to the electron beam during the measurement alter the original chemical bond state in these materials. Therefore, we are assessing the effect of different TEM sample preparation methods and beam conditions in a comparative study on [email protected] dielectric materials.

In its resolution of January I, 1985, the federal govemment of Germany deemed it necessary to develop, complementary to reprocessing, the direct disposal of spent fuel. The Deutsche Gesellschaft zum Bau und Betrieb von Endlagern fur Abfallstoffe was in charge of the implementation of demonstration tests aimed at proving the state of engineering readiness and planning of different repository concepts. Several repository alternatives (borehole emplacement, drift emplacement) including different waste pack-ages, cooling times, and technical equipment, etc., were compared. As a result, a reference and a backup concept were elaborated and subsequently examined in detail. Temperature calculations were carried out for a site-independent case andfor a case using the working model ofthe Gorleben salt dome, which displays a horizontal cut ofthe geological structure of the salt dome. The demonstration tests were intended for confirming technical feasibility under realistic conditions. They comprised simulation tests for shaft transport of heavy loads, handling tests of drift disposal, and active handling experiments with neutron sources.

Splitting of HOLZ lines on CBED patterns is systematically observed at the proximity of interfaces and prevents local strain measurements by monitoring of line shifts. It was previously suggested that such splitting occurs due to interface-strain relaxation in thin TEM lamella. Here we confirm this model by dynamical simulation of CBED patterns using the multislice algorithm.

The introduction of fragile ultralow-k materials as interlayer dielectrics in backend-of-line interconnect stacks asks for a thorough analysis of potential risks due to chip-package interaction. This paper shows how the application of several ex-situ and in-situ experimental approaches can be effectively used to assess such risks on the wafer level already at early stages of the development phase. The respective analytical techniques try to mimic chip-package interaction loading conditions. Most of the tests transfer loads to interconnect stacks via individual copper pillars. The investigations take place on the scale of about 100μm down to 1μm.

This study captures the time-dependent dielectric breakdown kinetics in nanoscale Cu/low-k interconnect structures, applying in-situ transmission electron microscopy (TEM) imaging and post-mortem electron spectroscopic imaging (ESI). A “tip-to-tip” test structure and an experimental methodology were established to observe the localized damage mechanisms under a constant voltage stress as a function of time. In an interconnect structure with partly breached barriers, in-situ TEM imaging shows Cu nanoparticle formation, agglomeration and movement in porous organosilicate glasses. In a flawless interconnect structure, in-situ TEM imaging and ESI mapping show close to no evidence of Cu diffusion in the TDDB process. From the ESI mapping, only a narrow Cu trace is found at the SiCN/OSG interface. In both cases, when barriers are breached or still intact, the initial damage is observed at the top interface of M1 between SiCN and OSG.

For thermal ALD Ta"xN"yC"z films improved growth behaviour and Cu diffusion barrier performance are demonstrated by applying a plasma treatment prior to film deposition, in particular on low-k dielectrics. Two different kinds of ALD processes for depositing thermal ALD Ta"xN"yC"z films are applied in this study, involving either TBTDET or PDMAT as a precursor. Ammonia is used as a reactant and Ar as a purging gas in both processes. Within the experiment, two types of pre-treatments prior to ALD are investigated: a wet-chemical pre-treatment using diluted (0.5%) HF, and plasma pre-treatments using Ar/H"2 or N"2 plasmas. It is examined by transmission electron microscopy (TEM) from a microstuctural perspective whether improved growth behaviour of thermal ALD Ta"xN"yC"z films can be achieved by applying a plasma treatment prior to film deposition. The Cu diffusion barrier properties of 10-15nm ALD TaNC films are then evaluated by bias temperature stress (BTS) and triangular voltage sweep (TVS) measurements on metal-insulator-semiconductor (MIS) test structures, after annealing at up to 600^oC under H"2/N"2 atmosphere. The results imply that, from a process side, thermal ALD TaNC films can intrinsically achieve a Cu diffusion barrier performance similar to PVD TaN. However, if no treatment was applied, Cu drift occurred.

This article deals with uncertainty in the analysis of strain in silicon nanoscale structures and devices using nanobeam electron diffraction (NBED). Specimen and instrument related errors and instabilities and their effects on NBED analysis are addressed using a nanopatterned ultrathin strained silicon layer directly on oxide as a model system. We demonstrate that zero-loss filtering significantly improves the NBED precision by decreasing the diffuse background in the diffraction patterns. To minimize the systematic deviations the acquired data were verified through a reliability test and then calibrated. Furthermore, the effect of strain relaxation by specimen preparation using a FIB is estimated by comparing profiles, which were acquired by analyzing slices of strained structures in a 220-nm-thick region of the sample (invasive preparation) and the entire strained nanostructures, which are embedded in a thicker region of the same sample (noninvasive preparation). Together with the random deviation, the corresponding systematic shift results in a total deviation of ∼1 × 10−3for NBED analyses, which is employed to estimate the measurement uncertainty in the thinner sample region. In contrast, the strain in the thick sample region is not affected by the preparation; the systematic shift reduces to a minimum, which improves the total deviation by ∼50%.

The aim of this work was to derive a model of the SCC crack growth mechanism from fractographic SEM investigations and from the results of crack tip characterisation work carried out in the TEM. The results refer to a microcrack induced gradual crack growth caused by local hydrogen embrittlement

Both process control and process development in the high performance semiconductor industry require more and more TEM analyses. This is mainly driven by the shrinkage in feature size and by the introduction of new material sets. As SEM analyses are executed routinely and in a high volume mode, the migration to TEM based analysis also requires high sample throughput. One throughput limiter in TEM analysis is sample drift after sample loading. It is not possible to perform high resolution TEM imaging or do analytical TEM work like EELS, EDX, Tomography, etc. before the thermal equilibrium inside the sample stage is achieved. Using improved FIB to TEM sample connectivity has significantly improved the time to thermal equilibrium, as well as enabling the move from 5% Liftout to more than 55% Lamella Liftout today.

Integration of compliant and brittle ultralow-k (ULK) interlayer dielectric (ILD) materials in advanced backend-of-line (BEOL) layer stacks requires a careful characterization of the mechanical stability of the BEOL stack to assure reliability during chip packaging and under field condition. We present a novel experimental technique which applies normal and shear forces on Cu pillars to test the stability of BEOL layer stacks beneath individual pillars. Critical forces and displacements are recorded with high sensitivity. The test directly verifies if the BEOL withstands the applied stress levels or if mechanical failure occurs.

The stress levels induced by chip‐package interaction (CPI) impose an increased risk of mechanical failure on advanced backend‐of‐line (BEOL) layer stacks in microelectronic circuits if they contain fragile ultralow‐k (ULK) interlayer dielectric (ILD) films. On the one hand, multilevel finite element modeling is used to assess the potential risk at an early stage of the development of new microelectronic products. On the other hand, the theoretical models need as accurate as possible materials parameters as an input to provide realistic results. Moreover, it is highly desirable to have multi‐scale experimental probes available which can provide complementary data to support the modeling calculations. The present paper provides an overview about various mechanical probing techniques which operate on the scale of less than 100 nm up to more than 100 μm. In this way, typical feature sizes are covered which occur from the package level via solder bumps or copper pillars down to small Cu/ULK interconnect structures. The experimental approaches are based on nanoindentation with lateral force detection and in‐situ scanning probe microscopy (SPM) imaging capabilities, and they include a novel technique named bump assisted BEOL stability indentation (BABSI) test. Especially, the interrelation between small‐scale mechanical properties of ULK dielectric films and stresses acting on larger scales are quantitatively assessed by means of the experimental approaches described here.

The influence of Ni-content of austenitic stainless steels on the SCC crack growth mechanism in chloride solutions at elevated temperatures is discussed, based on crack tip characterization of corrosive cracks by means of Transmission Electron Microscopy, Samples of stainless steels AISI 321 and INCOLOY 800 were analyzed. The results indicate a cracking process highly influenced by hydrogen, which is produced by the cathodic reaction of the corrosion process inside the crack.The effect of corrosive hydrogen on the cracking process depends on the stacking fault energy and thus on the Ni-content of the steel. There is also an influence of Ni-content on the diffusion coefficients of hydrogen in the austenitic lattic, determining the formation of hydrogen up to a critical concentration in the crack tip region

The introduction of future technology nodes is accompanied by further downscaling of the interconnect dimensions resulting in the growth of Cu grains with a grain size that is significantly smaller than 100 nm. Consequently, well established techniques for orientation imaging microscopy reach their resolution limit for sufficient Cu microstructure characterization. The only suitable alternative is given by transmission electron microscopy, and particularly, by applying the conical dark-field (CDF) technique which provides complete grain orientation maps. With a proven spatial resolution of better than 5 nm, various interconnect structures with Cu twins and agglomerates of small Cu grains are analyzed by the CDF technique.

Conical dark‐field (CDF) analysis in the transmission electron microscope is introduced as a suitable method for characterizing small Cu grains in advanced interconnect structures. With a proven spatial resolution in the

In this paper we showed results on high temperature storage tests performed on 90nm, 65nm and 45nm node material with different back end of line stacks. We have seen a strong impact of BEOL stack up on resistance traces of tests at temperature of over 250°C for 1000h. We found that the detected resistance increases are not related to stress migration phenomena but to changes in barrier integrity. The results suggest that the barrier is oxidizing due to oxygen supplied by the SiCOH ILD. First look into future technologies by adopted barrier processes simulating corresponding barrier thicknesses we see an acceleration of this results. Porous SiCOH which is used as baseline material for 45nm an beyond is even pronouncing this effect. This is definitely showing that this effect might become severe in future technologies.