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An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.

A Full-Band Capture (FBC) Harmonic Rejection Canceler (HRC) processor is presented. This processor consists of an RF low-noise preamplifier, a 2700 Msamp/s 6-bit flash ADC, a digital channelizer which selects one or more interfering RF channels, and an adaptive canceler. This canceler removes the interference caused by strong blockers that may be inadvertently folded onto the desired channel by local oscillator (LO) harmonics or spurs. This processor digitizes the entire cable or broadcast television spectrum from 50–1000 MHz and can adaptively cancel folded blocker interference from anywhere within this range. An image reduction of at least 23dB was measured. The processor is embedded within an integrated 40nm CMOS DVB-T2 TV receiver including tuner, demodulator and FEC. The complete embedded RF/analog/DSP HRC processor has an area of 0.38 mm2 and uses 205 mW.

The increased competition to deliver broadband data to the home (including GPON and VDSL) is motivating cable providers to deliver data rates which far exceed what is presently available based on the DOCSIS 1.x and DOCSIS 2.0 standards. The DOCSIS 3.0 standard provides this bandwidth increase as well as additional flexibility, where higher data throughput can be obtained by bonding together multiple downstream (DS) channels. This standard calls for the ability to bond any 4 channels in a 64MHz contiguous RF bandwidth. Solutions that allow even more channel bonding and provide more flexibility in the allocated frequency spectrum are preferred. This paper reports an embedded dual-tuner architecture able to select two independent 32MHz frequency bands, allowing for a maximum of 10 demodulated 6MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0MHz (CH 0), +6MHz (CH +1), +12MHz (CH +2), −6MHz (CH −1) and −12MHz (CH −2). Channels +1 and +2 lie at the images of channels −1 and −2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.

An ASIC implementation of a WCDMA mobile terminal with 2-dimensional adaptive antenna-rake combining is presented in this paper. System analysis shows that adaptive antenna-rake combining techniques can significantly enhance the performance and capacity of cellular systems compared to conventional CDMA systems. A hardware efficient receiver architecture is implemented supporting both maximal ratio combining (MRC) and least mean squares (LMS) algorithm. Moreover, the proposed architectures allows for a dynamic and flexible allocation of available processing resources (total of 20 fingers) to different antennas and multipaths based on the instantaneous channel profile. The presented receiver can operate in both normal and space time transmit diversity (STTD) modes. The system was implemented in a 0.18/spl mu/m CMOS process and the improvement was validated through real-time field trials.

An OFDM receiver ASIC targeting cellular terminals has been designed and fabricated in 0.18 /spl mu/m CMOS. The receiver incorporates a front-end receiver, pre/post-FFT processing units, a 1024-point complex (I)FFT processor, a channel estimator and corrector, all digital synchronization loops, and a control and configuration interface. Low power circuit techniques and system algorithm optimization lead to the final receiver ASIC that dissipates only 32 mW while providing a (uncoded) date-rate of 8.192 Mb/s, making the chip suitable for packet-based mobile applications.

A silicon implementation of a dual antenna mobile station modem for 3G WCDMA is presented. Diversity processing is used to support data rates up to 2 Mb/s while reducing power consumption. An average SNR improvement of 7 dB has been observed yielding up to a 4x increase in capacity with no change to the exisiting network infrastructure.

The proper choice of modulation and detection schemes to enable high-speed wireless indoor data communications has been the subject of extensive study. Of particular interest to ASIC designers is the complexity, cost and power dissipation of the analog and digital processing elements associated with such systems. This paper presents a side-by-side comparison of the three most popular system architectures for high-speed wireless data communications, namely equalized QPSK, equalized GMSK and OFDM. Their performance and minimum configuration at data rates up to 30 Mbps is measured and analyzed under a set of simulated indoor wireless channels with ensemble-average RMS delay spread /spl tau//sub RMS/ of 35 ns. The achievable channel capacity is proposed as a metric as well as outage and spectral efficiency. Finally, a single figure of merit is used to compare the three systems.

In this paper, we present the system design of an integrated receiver for the next generation high-speed mobile data communications based on OFDM. First an overview of the OFDM system suitable for mobile communications is described. The effects of non-ideal transmission conditions of the OFDM system including channel estimation errors, symbol timing offset, carrier and sampling clock offset, phase noise and time-selective fading are analyzed. We then propose an integrated receiver in which all of these issues relevant to the mobile transmission environment are addressed. Novel techniques for symbol timing and frequency synchronization are proposed. The architecture of the receiver and resulting implementation complexity are then analyzed. The overall performance degradation of the proposed receiver is simulated to be within 2-2.5 dB of the ideal receiver in various channel conditions.

This paper reports on field measurements of a highly versatile frequency-hopped (FH) frequency shift keyed (FSK) prototype operating in the 900 MHz ISM band and providing 160 kbps indoor wireless data communication. The testbed is used to study the impact of frequency hopping rate, channel spacing, diversity combining, and packet communication on frequency-hopped wireless transmission. Results are presented for 5,850 field trials of the testbed, programmed with different hopping configurations in three typical indoor environments. The measurement results underscore the dramatic potential of a system with fast hopping rates that employs equal gain hop combining with proper interleaving and frequency separation between hopping channels. However, fast hopping rate employed without diversity combining degrades symbol error rate (SER) almost linearly proportional to the hopping rate.