1. High performance Cu/low-k interconnect strategy beyond 10nm logic technology
- Author
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K.-M. Chung, Ju-Heon Kim, Byeong-Hee Kim, J-H Lee, H.-K. Kang, Youngwoo Cho, J. H. Hwang, Eung-joon Lee, Sang-Don Nam, Sung-yup Jung, Kwang-Myeon Park, J.W. Hwang, B. U. Yoon, Sang Hoon Ahn, Seungwook Choi, Rak-Hwan Kim, S. S. Paak, Jong-min Baek, S. Y. Yoo, E. S. Jung, S. H. Park, T.-J. Yim, Jang-ho Kim, Han-mei Choi, J.-H. Ku, T. Oszinda, J. Chang, Nae-In Lee, and I S. Kim
- Subjects
Interconnection ,Materials science ,Robustness (computer science) ,Electronic engineering ,Time-dependent gate oxide breakdown - Abstract
CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.
- Published
- 2015
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