1. A scalable optical neural network architecture using coherent detection
- Author
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Massachusetts Institute of Technology. Research Laboratory of Electronics, Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science, Sludds, Alexander, Bernstein, Liane, Hamerly, Ryan M, Soljacic, Marin, Englund, Dirk R., Massachusetts Institute of Technology. Research Laboratory of Electronics, Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science, Sludds, Alexander, Bernstein, Liane, Hamerly, Ryan M, Soljacic, Marin, and Englund, Dirk R.
- Abstract
© COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only. Storing, proceßing, and learning from data is a central task in both industrial practice and modern science. Recent advances in modern statistical learning, particularly Deep Neural Networks (DNNs), have given record breaking performance on tasks in game playing,1, 2 natural language proceßing,3 computer vision,4 computational biology,5, 6 and many others. The rapid growth of the field has been driven by an increase in the amount of public datasets,7 improvements to algorithms,8 and a substantial growth in computing power.9 In order to perform well on these tasks networks have had to grow in size, learning more complicated statistical features. The training and deployment of these large neural networks has spurred the creation of many neural network accelerators to aid in the computation of these networks.10-12 Existing general purpose computing devices such as CPUs and GPUs are limited both by thermal dißipation per unit area and yield aßociated with large chips.13, 14 The design of Application Specific Integrated circuits (ASICs) has aided in decreasing the energy consumption per workload substantially by limiting the supported operations on chip. An example of this is the first generation tensor proceßing unit (TPU)15 which is able to perform the inference of large convolutional neural networks in datacenter in <10ms with an idle power of 28W and an workload power of 40W. It may seen counterintuitive then that the limiting factor for the implementation of DNNs is not computation, but rather the energy and bandwidth aßociated with reading and writing data from memory as well as the energy cost of moving data inside of the ASIC.15, 16 Several emerging technologies, such as in-memory computing,17 memristive croßbar arrays18 promise increased performance, but these emerging architectures suffer from calibration ißues and limited accuracy.19 Photonics as a field has had tremendous succeß
- Published
- 2022