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We present preliminary results of theRooflineToolkit formulticore, manycore, and accelerated architectures. This paper focuses on the processor architecture characterization engine, a collection of portable instrumented micro benchmarks implemented with MessagePassing Interface (MPI), and OpenMP used to express thread-level parallelism. These benchmarks are specialized to quantify the behavior of different architectural features. Compared to previous work on performance characterization, these microbenchmarks focus on capturing the performance of each level of the memory hierarchy, along with thread-level parallelism, instruction-level parallelism and explicit SIMD parallelism, measured in the context of the compilers and run-time environments. We also measure sustained PCIe throughput with four GPU memory managed mechanisms. By combining results from the architecture characterization with the Roofline model based solely on architectural specifications, this work offers insights for performance prediction of current and future architectures and their software systems. To that end, we instrument three applications and plot their resultant performance on the corresponding Roofline model when run on a Blue Gene/Q architecture.

As shared-memory multiprocessor systems become widely available, there is an increasing need for tools to simplify the task of developing parallel programs. This paper describes one such tool, the automatic parallelization system in the Stanford SUIF compiler. This article represents a culmination of a several-year research effort aimed at making parallelizing compilers significantly more effective. We have developed a system that performs full interprocedural parallelization analyses, including array privatization analysis, array reduction recognition, and a suite of scalar dataflow analyses including symbolic analysis. These analyses collaborate in an integrated fashion to exploit coarse-grain parallel loops, computationally intensive loops that can execute on multiple processors independently with no cross-processor synchronization or communication. The system has successfully parallelized large interprocedural loops over a thousand lines of code completely automatically from sequential applications. This article provides a comprehensive description of the analyses in the SUIF system. We also present extensive empirical results on four benchmark suites, showing the contribution of individual analysis techniques both in executing more of the computation in parallel, and in increasing the granularity of the parallel computations. These results demonstrate the importance of interprocedural array data-flow analysis, array privatization and array reduction recognition; a third of the programs spend more than 50% of their execution time in computations that are parallelized with these techniques. Overall, these results indicate that automatic parallelization can be effective on sequential scientific computations, but only if the compiler incorporates all of these analyses. Categories and Subject Descriptors: C.1.2 [Processor Architectures]: Multiple Data Stream Architectures--array and vector processors; parallel processors; D.3.4 [Programming Languages]: compilers; optimization General Terms: Algorithms, Analysis, Experimentation, Performance Additional Key Words and Phrases: Data dependence analysis, interprocedural data-flow analysis, parallelization, symbolic analysis

A good memory system behavior is crucial in attaining speedups on moderate scale multiprocessors. Interactions between the compilers, parallel architectures and applications show that large granularity parallelism correlates with good performance, good memory system behavior and high speed. The use of long cache lines results in false sharing and low cache line utilization. The artifacts are also identified in compiler-parallelized codes which causes these false and true sharing. Small inner parallel loops are identified as the main source of trouble for poor memory behavior.

The compiler forms specialized copies of procedure bodies during procedure cloning, which is an interprocedural transformation. The compiler separates the incoming calls between the original procedure and the copies. The inheritance of an environment by each clone enables better code optimization. The clone procedure is decided by a three-phase algorithm. Unnecessary code growth is avoided by the algorithm by considering the information exposure of cloning during optimization.

The results of an evaluation of automatic parallelization in the Stanford SUIF compiler that exploits loop-level parallelism on shared memory multiprocessor architectures are presented.