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The multifaceted, multivendor-based global design supply chain induces hardware threats of intellectual property (IP) piracy for modern computing and electronic systems. Current hardware watermarking techniques fall short either in terms of watermark strength (size of covert constraints generated) or number of security layers/variables involved in the security constraints generation process. This paper presents a novel approach for high level synthesis (HLS) watermarking by bio-mimicking DNA fingerprint profiling to counter hardware IP piracy. The proposed approach effectively captures the vital DNA fingerprint profiling phases such as DNA sequencing, DNA fragmentation, fragment replication, DNA ligase, etc. and bio-mimics them to generate a digital watermarking framework. The presented approach has been demonstrated on convolutional layer and JPEG compression-decompression (CODEC) algorithms that are widely used in several medical and machine learning applications. The proposed approach has been thoroughly compared with several state-of-the-art approaches. The proposed approach depicts superior security in the probability of coincidence of up to ~ 104 and tamper tolerance of up to ~ 10368 at 0% overhead as compared to the prior approaches. [ABSTRACT FROM AUTHOR]

Savannas are widespread biomes with highly valued ecosystem services. To successfully manage savannas in the future, it is critical to better understand the long-term dynamics of their productivity and phenology. However, accurate large-scale gross primary productivity (GPP) estimation remains challenging because of the high spatial and seasonal variations in savanna GPP. China's savanna ecosystems constitute only a small part of the world's savanna ecosystems and are ecologically fragile. However, studies on GPP and phenological changes, while closely related to climate change, remain scarce. Therefore, we simulated savanna ecosystem GPP via a satellite-based vegetation photosynthesis model (VPM) with fine-resolution harmonized Landsat and Sentinel-2 (HLS) imagery and derived savanna phenophases from phenocam images. From 2015 to 2018, we compared the GPP from HLS VPM (GPPHLS-VPM) simulations and that from Moderate-Resolution Imaging Spectroradiometer (MODIS) VPM simulations (GPPMODIS-VPM) with GPP estimates from an eddy covariance (EC) flux tower (GPPEC) in Yuanjiang, China. Moreover, the consistency of the savanna ecosystem GPP was validated for a conventional MODIS product (MOD17A2). This study clearly revealed the potential of the HLS VPM for estimating savanna GPP. Compared with the MODIS VPM, the HLS VPM yielded more accurate GPP estimates with lower root-mean-square errors (RMSEs) and slopes closer to 1:1. Specifically, the annual RMSE values for the HLS VPM were 1.54 (2015), 2.65 (2016), 2.64 (2017), and 1.80 (2018), whereas those for the MODIS VPM were 3.04, 3.10, 2.62, and 2.49, respectively. The HLS VPM slopes were 1.12, 1.80, 1.65, and 1.27, indicating better agreement with the EC data than the MODIS VPM slopes of 2.04, 2.51, 2.14, and 1.54, respectively. Moreover, HLS VPM suitably indicated GPP dynamics during all phenophases, especially during the autumn green-down period. As the first study that simulates GPP involving HLS VPM and compares satellite-based and EC flux observations of the GPP in Chinese savanna ecosystems, our study enables better exploration of the Chinese savanna ecosystem GPP during different phenophases and more effective savanna management and conservation worldwide. [ABSTRACT FROM AUTHOR]

Abstract The multifaceted, multivendor-based global design supply chain induces hardware threats of intellectual property (IP) piracy for modern computing and electronic systems. Current hardware watermarking techniques fall short either in terms of watermark strength (size of covert constraints generated) or number of security layers/variables involved in the security constraints generation process. This paper presents a novel approach for high level synthesis (HLS) watermarking by bio-mimicking DNA fingerprint profiling to counter hardware IP piracy. The proposed approach effectively captures the vital DNA fingerprint profiling phases such as DNA sequencing, DNA fragmentation, fragment replication, DNA ligase, etc. and bio-mimics them to generate a digital watermarking framework. The presented approach has been demonstrated on convolutional layer and JPEG compression-decompression (CODEC) algorithms that are widely used in several medical and machine learning applications. The proposed approach has been thoroughly compared with several state-of-the-art approaches. The proposed approach depicts superior security in the probability of coincidence of up to ~ 104 and tamper tolerance of up to ~ 10368 at 0% overhead as compared to the prior approaches.

Nowadays, establishing security in data transmission is essential, and it is achieved by cryptography. Encryption of still or video images in specific applications such as Internet of Things, medical and satellite imaging, in applications requiring high-speed encryption, or even in applications where a personal computer is unavailable or cannot be used needs special hardware. In this paper, an image encryption algorithm based on chaos theory named Parallel Chaotic Checksum-based Image Encryption or PCCIE algorithm is proposed that has been able to provide a fast, efficient and secure algorithm with a hardware perspective on the design and parallel system structure. Using high-level synthesis, PCCIE is implemented on a Field Programmable Gate Array (FPGA). The proposed algorithm using small and independent local image buffers solved FPGA internal memory limitation for encryption of large images. Ultimately, a Hexa-core crypto-processor with single-precision floating-point and fixed-point precision has been designed, capable of encrypting 256 × 256 and Full HD images in 2.13 and 59.52 milliseconds, respectively, at 469 and 16 frames per second. [ABSTRACT FROM AUTHOR]

This study presents a hardware-software co-design implementation of an accelerator for the Kernelized Correlation Filter (KCF) tracking algorithm. Leveraging High-Level Synthesis (HLS) and the Zynq heterogeneous platform, the KCF algorithm's performance is enhanced by using a custom hardware implementation for the computationally intensive Discrete Fourier Transform (DFT) operation. Within this framework, a custom combined DFT and inverse DFT IP, named CDFT, is developed and optimized on the Programmable Logic (PL) side of the Xilinx ZCU102 FPGA, whereas the rest of the KCF algorithm is run with customized Petalinux build on the (Processing System) side. To assess real-world performance, a driver for the CDFT IP and a user application were created to measure metrics like Center Location Error (CLE), Intersection over Union (IoU), and Frame per Second (FPS). The designed DFT accelerator achieves a remarkable speedup of 21x compared to a software DFT implementation. At the algorithm level, the KCF accelerator obtains a 6x speed up with negligible precision loss. In comparison to prior studies employing exclusively hardware implementations, the proposed approach demonstrates a high accuracy at a moderate speed, while there exists potential for further optimizations to enhance its performance even further. [ABSTRACT FROM AUTHOR]

Spiking Neural Networks (SNNs) are models that mimic and replicate the computational properties of the biological brain. Computation is performed using neurons that transmit information on axons between each other via synapses. SNNs have several important application areas, ranging from (brain-like) artificial intelligence to complex brain simulations. Most SNN simulations today are carried out on systems such as CPUs and GPUs, which fit SNNs poorly and often yield slow solutions that consume needlessly much energy. In this work, we present algorithms for efficient simulation of SNNs on Field-Programmable Gate Arrays (FPGAs), which is driven by our hypothesis that said devices can be much more power-efficient without sacrificing execution performance. We also provide an in-depth analysis and discussion of our algorithms and techniques. We target the important Potjans-Diesmann model, a well-known cortical microcircuit often used for assessing SNN simulation performance. Using high-level synthesis (HLS) targeting the latest Intel Agilex 7 FPGA, we show that our best simulator can execute the microcircuit 25% faster than real-time and require only 21 nJ per synaptic event. Our result surpasses the state-of-the-art for single-device simulation, and the energy use is the lowest among published results. We have published our implementation at https://github.com/bjourne/fast_snn_fpga.

Savannas are widespread biomes with highly valued ecosystem services. To successfully manage savannas in the future, it is critical to better understand the long-term dynamics of their productivity and phenology. However, accurate large-scale gross primary productivity (GPP) estimation remains challenging because of the high spatial and seasonal variations in savanna GPP. China’s savanna ecosystems constitute only a small part of the world’s savanna ecosystems and are ecologically fragile. However, studies on GPP and phenological changes, while closely related to climate change, remain scarce. Therefore, we simulated savanna ecosystem GPP via a satellite-based vegetation photosynthesis model (VPM) with fine-resolution harmonized Landsat and Sentinel-2 (HLS) imagery and derived savanna phenophases from phenocam images. From 2015 to 2018, we compared the GPP from HLS VPM (GPPHLS-VPM) simulations and that from Moderate-Resolution Imaging Spectroradiometer (MODIS) VPM simulations (GPPMODIS-VPM) with GPP estimates from an eddy covariance (EC) flux tower (GPPEC) in Yuanjiang, China. Moreover, the consistency of the savanna ecosystem GPP was validated for a conventional MODIS product (MOD17A2). This study clearly revealed the potential of the HLS VPM for estimating savanna GPP. Compared with the MODIS VPM, the HLS VPM yielded more accurate GPP estimates with lower root-mean-square errors (RMSEs) and slopes closer to 1:1. Specifically, the annual RMSE values for the HLS VPM were 1.54 (2015), 2.65 (2016), 2.64 (2017), and 1.80 (2018), whereas those for the MODIS VPM were 3.04, 3.10, 2.62, and 2.49, respectively. The HLS VPM slopes were 1.12, 1.80, 1.65, and 1.27, indicating better agreement with the EC data than the MODIS VPM slopes of 2.04, 2.51, 2.14, and 1.54, respectively. Moreover, HLS VPM suitably indicated GPP dynamics during all phenophases, especially during the autumn green-down period. As the first study that simulates GPP involving HLS VPM and compares satellite-based and EC flux observations of the GPP in Chinese savanna ecosystems, our study enables better exploration of the Chinese savanna ecosystem GPP during different phenophases and more effective savanna management and conservation worldwide.

This paper investigates a real-time process generator of wideband signals, which calculates waveforms in a field-programmable gate array (FPGA) using the high-level synthesis (HLS) method. To obtain high-resolution and wide-swath images, the generator must produce multiple modes of large time-bandwidth product (TBP) linear frequency modulation (LFM) signals. However, the conventional storage method is unrealistic as it requires huge storage resources to save pre-computed waveforms. Therefore, this paper proposes a novel processing approach that calculates waveforms in real-time based simply on parameters such as the sampling frequency, bandwidth, and time width. Additionally, this paper implements predistortion through the polynomial curve to approximate phase errors of the system. The parallelizing process in the FPGA is necessary to satisfy the high-speed requirement of a digital-to-analog converter (DAC); however, repeatedly multiplexing real-time calculation consumes extensive logic and DSP resources, potentially exceeding FPGA limitations. To address this, this paper proposes a piecewise linear algorithm to conserve resources, which processes the polynomial only once, acquires the difference in two adjacent values through the register and pipeline, and then adds this increment to facilitate parallel computations. The performance of this proposed generator is validated through simulation and implemented in experiments with an X-band airborne SAR system. [ABSTRACT FROM AUTHOR]

Field-programmable gate array (FPGA)--based accelerators are becoming increasingly popular for deep neural network (DNN) inference due to their ability to scale performance with increasing degrees of specialization with dataflow architectures or custom data type precision. In order to reduce the barrier for software engineers and data scientists to adopt FPGAs, C++- and OpenCL-based design entries with high-level synthesis (HLS) have been introduced. They provide higher abstraction compared with register-transfer level (RTL)--based design. HLS offers faster development time, better maintainability, and more flexibility in code exploration when evaluating several options for multi-dimension tensors, convolutional layers, or different degrees of parallelism. For this reason, HLS has been adopted by DNN accelerator generation frameworks such as FINN and hls4ml. In this article, we present an alternative backend library for FINN, leveraging RTL. We investigate and evaluate, across a spectrum of design dimensions, the pros and cons of an RTL-based implementation versus the original HLS variant. We show that for smaller design parameters, RTL produces significantly smaller circuits as compared with HLS. For larger circuits, however, the look-up table (LUT) count of RTL-based design is slightly higher, up to around 15%. On the other hand, HLS consistently requires more flip-flops (FFs; with an orders-of-magnitude difference for smaller designs) and block RAMs (BRAMs; 2x more). This also impacts the critical path delay, with RTL producing significantly faster circuits, up to around 80%. RTL also benefits from at least a 10x reduction in synthesis time. Finally, the results were validated in practice using two real-world use cases, one of a multi-layer perceptron (MLP) used in network intrusion detection and the other a convolution network called ResNet, used in image recognition. Overall, since HLS frameworks code-generate the hardware design, the benefits of the ease in the design entry is less important. As such, the gained benefits in synthesis time together with some design-dependent resource benefits make the RTL abstraction an attractive alternative. [ABSTRACT FROM AUTHOR]

Hypothesis: The behavior of Heterogeneous Lyophobic Systems (HLSs) comprised of a lyophobic porous material and a corresponding non-wetting liquid is affected by a variety of different structural parameters of the porous material. Dependence on exogenic properties such as crystallite size is desirable for system tuning as they are much more facilely modified. We explore the dependence of intrusion pressure and intruded volume on crystallite size, testing the hypothesis that the connection between internal cavities and bulk water facilitates intrusion via hydrogen bonding, a phenomenon that is magnified in smaller crystallites with a larger surface/volume ratio. Experiments: Water intrusion/extrusion pressures and intrusion volume were experimentally measured for ZIF-8 samples of various crystallite sizes and compared to previously reported values. Alongside the practical research, molecular dynamics simulations and stochastic modeling were performed to illustrate the effect of crystallite size on the properties of the HLSs and uncover the important role of hydrogen bonding within this phenomenon. Findings: A reduction in crystallite size led to a significant decrease of intrusion and extrusion pressures below 100 nm. Simulations indicate that this behavior is due to a greater number of cages being in proximity to bulk water for smaller crystallites, allowing cross-cage hydrogen bonds to stabilize the intruded state and lower the threshold pressure of intrusion and extrusion. This is accompanied by a reduction in the overall intruded volume. Simulations demonstrate that this phenomenon is linked to ZIF-8 surface half-cages exposed to water being occupied by water due to non-trivial termination of the crystallites, even at atmospheric pressure. [ABSTRACT FROM AUTHOR]

Image processing is becoming more popular because images are being used increasingly in medical diagnosis, biometric monitoring, and character recognition. But these images are frequently contaminated with noise, which can corrupt subsequent image processing stages. Therefore, in this paper, we propose a novel nonlinear filter for removing "salt and pepper" impulsive noise from a complex color image. The new filter is called the Modified Vector Directional Filter (MVDF). The suggested method is based on the traditional Vector Directional Filter (VDF). However, before the candidate pixel is processed by the VDF, theMVDF employs a threshold and the neighboring pixels of the candidate pixel in a 3×3 filter window to determine whether it is noise-corrupted or noise-free. Several reference color images corrupted by impulsive noise with intensities ranging from 3% to 20% are used to assess theMVDF's effectiveness. The results of the experiments show that theMVDF is better than the VDF and the Generalized VDF (GVDF) in terms of the PSNR (Peak Signal-to-Noise Ratio), NCD (Normalized Color Difference), and execution time for the denoised image. In fact, the PSNR is increased by 6.554% and 12.624%, the NCD is decreased by 20.273% and 44.147%, and the execution time is reduced by approximately a factor of 3 for the MVDF relative to the VDF and GVDF, respectively. These results prove the efficiency of the proposed filter. Furthermore, a hardware design is proposed for the MVDF using the High-Level Synthesis (HLS) flow in order to increase its performance. This design, which is implemented on the Xilinx ZynqXCZU9EG Field-ProgrammableGate Array (FPGA), allows the restoration of a 256×256-pixel image in 2 milliseconds (ms) only. [ABSTRACT FROM AUTHOR]

Agricultural intensification practices have been adopted in the Brazilian savanna (Cerrado), mainly in the transition between Cerrado and the Amazon Forest, to increase productivity while reducing pressure for new land clearing. Due to the growing demand for more sustainable practices, more accurate information on geospatial monitoring is required. Remote sensing products and artificial intelligence models for pixel-by-pixel classification have great potential. Therefore, we developed a methodological framework with spectral indices (Normalized Difference Vegetation Index (NDVI), Normalized Difference Water Index (NDWI), and Soil-Adjusted Vegetation Index (SAVI)) derived from the Harmonized Landsat Sentinel-2 (HLS) and machine learning algorithms (Random Forest (RF), Artificial Neural Networks (ANNs), and Extreme Gradient Boosting (XGBoost)) to map agricultural intensification considering three hierarchical levels, i.e., temporary crops (level 1), the number of crop cycles (level 2), and the crop types from the second season in double-crop systems (level 3) in the 2021–2022 crop growing season in the municipality of Sorriso, Mato Grosso State, Brazil. All models were statistically similar, with an overall accuracy between 85 and 99%. The NDVI was the most suitable index for discriminating cultures at all hierarchical levels. The RF-NDVI combination mapped best at level 1, while at levels 2 and 3, the best model was XGBoost-NDVI. Our results indicate the great potential of combining HLS data and machine learning to provide accurate geospatial information for decision-makers in monitoring agricultural intensification, with an aim toward the sustainable development of agriculture. [ABSTRACT FROM AUTHOR]

Spatially and temporally precise monitoring of forest resources is becoming increasingly vital in rapidly changing environmental and economic conditions. However, recent developments in moderate resolution satellite imagery have led to spectrally consistent and temporally dense datasets capable of capturing both seasonal variation and long-term trajectories. Previous studies have demonstrated the ability of continuous monitoring algorithms to detect transitional changes such as timber harvesting at sub-annual scales. However, less is known about the ability to use these algorithms in areas such as high-latitude forests which have large data gaps over winter due to prolonged snow cover. This study investigated the use of a time series of 7-day Harmonized Landsat Sentinel-2 (HLS) composites along with the Bayesian Estimator of Abrupt Change, Seasonality, and Trend (BEAST) algorithm for change detection and monitoring in two managed forest areas in Canada. On average, both sites had no data periods (over winter) lasting ∼200 days. Despite this, BEAST successfully detected change, with overall accuracies of 88.7% and 97.3% for both sites when compared to an independent validation dataset derived from visual interpretation of PlanetScope images. A simulation of change detection in near-real time revealed that approximately 75% of changes were detected within 7 and 11 valid images for each site. Furthermore, monitoring the trend slope of the spectral index showed that areas with a new declining slope were typically about twice as likely to occur in photointerpreted polygons of non-stand replacing disturbance, indicating that such a technique could be used as an early warning signal of fine-scale changes such as those due to insect defoliation or drought. Overall, this study demonstrated the efficacy of a continuous change detection and monitoring framework, which could be used to provide insights at previously unavailable temporal and spatial scales, thereby allowing forest managers the ability to quickly react to changes in uncertain future conditions. [ABSTRACT FROM AUTHOR]

In this paper we propose SECDA-TFLite, a new open source toolkit for developing DNN hardware accelerators integrated within the TFLite framework. The toolkit leverages the principles of SECDA, a hardware/software co-design methodology, to reduce the design time of optimized DNN inference accelerators on edge devices with FPGAs. With SECDA-TFLite, we reduce the initial setup costs associated with integrating a new accelerator design within a target DNN framework, allowing developers to focus on the design. SECDA-TFLite also includes modules for cost-effective SystemC simulation, profiling, and AXI-based data communication. As a case study, we use SECDA-TFLite to develop and evaluate three accelerator designs across seven common CNN models and two BERT-based models against an ARM A9 CPU-only baseline, achieving an average performance speedup across models of up to 3.4× for the CNN models and of up to 2.5× for the BERT-based models. Our code is available at https://github.com/gicLAB/SECDA-TFLite. • We propose SECDA-TFLite, a toolkit for efficient development of FPGA-based accelerators for DNN edge inference on TFLite. • We port two previously hardware accelerators for quantized CNN inference with TFLite. • We develop a new hardware accelerator for quantized BERT inference with TFLite. • We evaluate the CNN accelerators on five popular CNN models achieving up to 2.5x speedup. • We evaluate the BERT accelerator on MobileBert and Albert models achieving up to 2.9x speedup. [ABSTRACT FROM AUTHOR]

This paper investigates a real-time process generator of wideband signals, which calculates waveforms in a field-programmable gate array (FPGA) using the high-level synthesis (HLS) method. To obtain high-resolution and wide-swath images, the generator must produce multiple modes of large time-bandwidth product (TBP) linear frequency modulation (LFM) signals. However, the conventional storage method is unrealistic as it requires huge storage resources to save pre-computed waveforms. Therefore, this paper proposes a novel processing approach that calculates waveforms in real-time based simply on parameters such as the sampling frequency, bandwidth, and time width. Additionally, this paper implements predistortion through the polynomial curve to approximate phase errors of the system. The parallelizing process in the FPGA is necessary to satisfy the high-speed requirement of a digital-to-analog converter (DAC); however, repeatedly multiplexing real-time calculation consumes extensive logic and DSP resources, potentially exceeding FPGA limitations. To address this, this paper proposes a piecewise linear algorithm to conserve resources, which processes the polynomial only once, acquires the difference in two adjacent values through the register and pipeline, and then adds this increment to facilitate parallel computations. The performance of this proposed generator is validated through simulation and implemented in experiments with an X-band airborne SAR system.

In recent years, edge intelligence (EI) has emerged, combining edge computing with AI, and specifically deep learning, to run AI algorithms directly on edge devices. In practical applications, EI faces challenges related to computational power, power consumption, size, and cost, with the primary challenge being the trade-off between computational power and power consumption. This has rendered traditional computing platforms unsustainable, making heterogeneous parallel computing platforms a crucial pathway for implementing EI. In our research, we leveraged the Xilinx Zynq 7000 heterogeneous computing platform, employed high-level synthesis (HLS) for design, and implemented two different accelerators for LeNet-5 using loop unrolling and pipelining optimization techniques. The experimental results show that when running at a clock speed of 100 MHz, the PIPELINE accelerator, compared to the UNROLL accelerator, experiences an 8.09% increase in power consumption but speeds up by 14.972 times, making the PIPELINE accelerator superior in performance. Compared to the CPU, the PIPELINE accelerator reduces power consumption by 91.37% and speeds up by 70.387 times, while compared to the GPU, it reduces power consumption by 93.35%. This study provides two different optimization schemes for edge intelligence applications through design and experimentation and demonstrates the impact of different quantization methods on FPGA resource consumption. These experimental results can provide a reference for practical applications, thereby providing a reference hardware acceleration scheme for edge intelligence applications.

The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to solve this drawback. However, using traditional hardware description language (HDL) to implement FPGA-based accelerators requires a high design time. Fortunately, the open computing language (OpenCL) high level parallel programming tool allows rapid and effective design on FPGA-based hardware accelerators. In this study, OpenCL has been used to examine speeding up the DCT-KNN algorithm on the FPGA parallel computing platform through applying numerous parallelization and optimization techniques. The optimized approach of the improved KNN could be used in various engineering problems that require a high speed of classification process. Classification of the COVID-19 disease is the case study used to examine this work. The experimental results show that implementing the DCT-KNN algorithm on the FPGA platform (Intel De5a-net Arria-10 device was used) gives an extremely high performance when compared to the traditional single-core-CPU based implementation. The execution time for our optimized design on the FPGA accelerator is 44 times faster than the conventional design implemented on the regular CPU-based computational platform.

Fuzzy Logic Controllers (FLC) are control systems commonly used on problems where data is not accurate or its domain is not well-known. This is because instead of using complex mathematical models to work, they use a set of rules to evaluate data. To implement this kind of controllers one interesting option is FPGA. This technology has advantages based on reconfigurability, performance, energy usage and design flexibility. This work presents a tool based on HLS and FPGA that allows users to generate Fuzzy Logic Controllers from abstract descriptions. Also the most impactful synthesis directives for optimizing the different stages of a FLC are detailed. Finally, three case studies are presented to evaluate the tool.

An efficient parasite control reduces significant losses in the agribusiness, but current methods involve costs and delays. Therefore, the development of a portable device to automates this task is proposed. This work presents a hardware implementation of an automatic parasite egg counting algorithm using high-level synthesis. The results demonstrate the feasibility of the implementation, with an 87% accuracy operating at a rate of up to 65 frames per second and an occupation of LUTs less than 45%, considering two commercial kits (PYNQ-Z1 and ULTRA96V2).

FPGA-based cards for data concentration and readout are often used in data acquisition (DAQ) systems for high-energy physics experiments. The DMA engines implemented in FPGA enable efficient data transfer to the processing system's memory. This paper presents a versatile DMA engine. It may be used in systems with FPGA-equipped PCIe boards hosted in a server and MPSoC-based systems with programmable logic connected directly to the AXI system bus. The core part of the engine is implemented in HLS to simplify further development and modifications. The design is modular and may be easily integrated with the user's DAQ logic, assuming it delivers the data via a standard AXI-Stream interface. The engine and accompanying software are designed with flexibility in mind. They offer a simple single-packet mode for debugging and a high-performance multi-packet mode fully utilizing the computational power of the processing system. The number of used DAQ cards and the amount of memory used for the DMA buffer may be modified in the runtime without rebooting the system. That is particularly useful in the development and test setups. This paper also presents the development and testing methodology. The whole design is open-source and available in public repositories. [ABSTRACT FROM AUTHOR]

Different initiatives for mapping land use and land cover using orbital remote sensing have been carried out with the aim of supporting agri-environmental planning in the Brazilian Savanna (Cerrado). However, the complex regional agricultural dynamics require more detail in the discrimination of agricultural uses, which requires time series of satellite images (SITS). This study aimed to evaluate how the integrated use of Landsat 8 Operational Land Imager (OLI) and Sentinel-2 Multispectral Instrument data can contribute to digital land use and land cover mapping in medium spatial resolution. The municipality of Balsas, a region of agricultural expansion in the Cerrado of Maranhão State and relevant economic and agro-environmental interest, was chosen as a study area to evaluate the performance of Random Forest classification models generated with data from Landsat 8, Sentinel-2, and the Harmonized Landsat Sentinel 2 (HLS). The MSI, HLS, and OLI models presented similar performance, with Global precision of 0.857, 0.844, and 0.832, and Kappa index of 0.819, 0.803, and 0.787, respectively. The T-Test indicated that these results are not statistically different. However, despite the models' performance, the final map created with the OLI data showed a high loss of information due to the absence of pixels in the time series. The new HLS data proved suitable for land use and coverage mapping, even on a large scale, at a resolution of 30 m, with precision and reduced processing time compared to the MSI data. These results can support decision-making in the planning and execution of new agricultural mapping of the Cerrado Biome. [ABSTRACT FROM AUTHOR]

FPGAs, characterized by their low power consumption and swift response, are ideally suited for parallel computations associated with object detection tasks, making them a popular choice for target detection and neural network acceleration. However, contemporary FPGA designs often come with high costs and resource demands, which limit their adoption in resource-constrained embedded and edge devices. This study presents a novel design that addresses these limitations by emphasizing cost-effectiveness, energy efficiency, and rapid performance, particularly for single-shot multi-box detectors. The design employs an Xilinx ZYNQ7020-based main control chip and leverages parallel computing models for convolution layers and feature extraction. It enhances efficiency by proposing parallel feature extraction at the network architecture level and integrates convolution activation and pooling in a single, hardware-optimized operation for convolution kernel computations. The design employs alternating memory reuse for feature layer inputs and outputs to optimize memory management, thereby reducing read/write delays and transmission times. Implemented on a PYNQ-Z2 development board and tested using Jupyter Notebook, the SSD algorithm demonstrates a 789.4 GOPS inference performance with 16-bit fixed-point quantization at a 200MHz clock frequency, achieving an average accuracy of 77.84% and an inference time of 81.4621 ms, while consuming 1.595 watts of power. This innovative design significantly boosts energy efficiency by up to 2590%, outperforming contemporary methods. • Parallel computation boosts speed and efficiency in convolutional layers. • Integrated parallel processing enhances convolution activation pooling. • Efficient memory management reduces read/write time for feature layers. • Implemented on PYNQ-Z2 with FPGA hardware using high-level synthesis. • Achieved 77.84% precision, 81.4621 ms inference time, 2590% energy efficiency gain. [ABSTRACT FROM AUTHOR]

Efficient lattice-based cryptosystems operate with polynomial rings with the Number Theoretic Transform (NTT) to reduce the computational complexity of polynomial multiplication. NTT has therefore become a major arithmetic component (thus computational bottleneck) in various cryptographic constructions like hash functions, key-encapsulation mechanisms, digital signatures, and homomorphic encryption. Although there exist several hardware designs in prior work for NTT, they all are isolated design instances fixed for specific NTT parameters or parallelization level. This article provides an extensive study of flexible design methods for NTT implementation. To that end, we evaluate three cases: (1) parametric hardware design, (2) high-level synthesis (HLS) design approach, and (3) design for software implementation compiled on soft-core processors, where all are targeted on reconfigurable hardware devices. We evaluate the designs that implement multiple NTT parameters and/or processing elements, demonstrate the design details for each case, and provide a fair comparison with each other and prior work. On a Xilinx Virtex-7 FPGA, compared to HLS and processor-based methods, the results show that the parametric hardware design is on average $4.4\times$ 4. 4 × and $73.9\times$ 73. 9 × smaller and $22.5\times$ 22. 5 × and $19.3\times$ 19. 3 × faster, respectively. Surprisingly, HLS tools can yield less efficient solutions than processor-based approaches in some cases. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new Modified Laplacian Vector Median Filter (MLVMF) for real-time denoising complex images corrupted by "salt and pepper" impulsive noise. The method consists of two rounds with three steps each: the first round starts with the identification of pixels that may be contaminated by noise using a Modified Laplacian Filter. Then, corrupted pixels pass a neighborhood-based validation test. Finally, the Vector Median Filter is used to replace noisy pixels. The MLVMF uses a 5 × 5 window to observe the intensity variations around each pixel of the image with a rotation step of π/8 while the classic Laplacian filters often use rotation steps of π/2 or π/4. We see better identification of noise-corrupted pixels thanks to this rotation step refinement. Despite this advantage, a high percentage of the impulsive noise may cause two or more corrupted pixels (with the same intensity) to collide, preventing the identification of noise-corrupted pixels. A second round is then necessary using a second set of filters, still based on the Laplacian operator, but allowing focusing only on the collision phenomenon. To validate our method, MLVMF is firstly tested on standard images, with a noise percentage varying from 3% to 30%. Obtained performances in terms of processing time, as well as image restoration quality through the PSNR (Peak Signal to Noise Ratio) and the NCD (Normalized Color Difference) metrics, are compared to the performances of VMF (Vector Median Filter), VMRHF (Vector Median-Rational Hybrid Filter), and MSMF (Modified Switching Median Filter). A second test is performed on several noisy chest x-ray images used in cardiovascular disease diagnosis as well as COVID-19 diagnosis. The proposed method shows a very good quality of restoration on this type of image, particularly when the percentage of noise is high. The MLVMF provides a high PSNR value of 5.5% and a low NCD value of 18.2%. Finally, an optimized Field-Programmable Gate Array (FPGA) design is proposed to implement the proposed method for real-time processing. The proposed hardware implementation allows an execution time equal to 9 ms per 256 × 256 color image. [ABSTRACT FROM AUTHOR]

Agricultural intensification practices have been adopted in the Brazilian savanna (Cerrado), mainly in the transition between Cerrado and the Amazon Forest, to increase productivity while reducing pressure for new land clearing. Due to the growing demand for more sustainable practices, more accurate information on geospatial monitoring is required. Remote sensing products and artificial intelligence models for pixel-by-pixel classification have great potential. Therefore, we developed a methodological framework with spectral indices (Normalized Difference Vegetation Index (NDVI), Normalized Difference Water Index (NDWI), and Soil-Adjusted Vegetation Index (SAVI)) derived from the Harmonized Landsat Sentinel-2 (HLS) and machine learning algorithms (Random Forest (RF), Artificial Neural Networks (ANNs), and Extreme Gradient Boosting (XGBoost)) to map agricultural intensification considering three hierarchical levels, i.e., temporary crops (level 1), the number of crop cycles (level 2), and the crop types from the second season in double-crop systems (level 3) in the 2021–2022 crop growing season in the municipality of Sorriso, Mato Grosso State, Brazil. All models were statistically similar, with an overall accuracy between 85 and 99%. The NDVI was the most suitable index for discriminating cultures at all hierarchical levels. The RF-NDVI combination mapped best at level 1, while at levels 2 and 3, the best model was XGBoost-NDVI. Our results indicate the great potential of combining HLS data and machine learning to provide accurate geospatial information for decision-makers in monitoring agricultural intensification, with an aim toward the sustainable development of agriculture.