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We present a theoretical explanation of the interfacial component in the gate resistance of Schottky-barrier-gate field-effect transistors (SBGFETs). This component was recently established and was found, for GaAs- and InP-based SBGFETs, to have the smallest practically achievable normalized value ${r}_{\mathrm{gi}}$ on the order of ${10}^{\ensuremath{-}7} \ensuremath{\Omega}{\mathrm{cm}}^{2}.$ We show that ${r}_{\mathrm{gi}}$ in this range can be modeled as an ac tunneling resistance ${r}_{\mathrm{IT}}$ between the three-dimensional (3D) gate metal and the 2D semiconductor surfaces states. We extend Cowley and Sze's static Schottky-barrier lineup model to include high-frequency modulation of the surface-state occupation by an ac gate voltage. We find that, since ${r}_{\mathrm{IT}}$ is not simply a dc resistance in series with the standard parasitic gate resistance, the resulting experimentally observed ${r}_{\mathrm{gi}}$ is smaller by an amount that depends on the interfacial layer and surface-state density. However, for the typically observed values, ${r}_{\mathrm{gi}}$ acts like a series resistance up to presently attainable frequencies. Thus, while Cowley and Sze's phenomenological ``interfacial layer of the order of atomic dimensions'' is more or less ``transparent to electrons,'' it presents a resistance that cannot be ignored at microwave and millimeter-wave frequencies. We apply our theory using interfacial-layer parameter values corresponding to alternative models for Schottky-barrier formation, and compare the predictions to experimental observations. Our results are consistent with models that involve defects near the semiconductor-metal interface.

An application-ready prescaler with performance competitive with state-of-the-art R&D dividers was designed to be a high-performance replacement for standard ECL parts in instruments. It is fabricated in a proven self-aligned contact sub-half-micrometer GaAs-based enhancement/depletion-mode (E/D-mode) MODFET IC process that utilizes sidewall-spacer self-alignment technology to obtain 0.3-0.5 mu m gate length with conventional high-throughput contact lithography. With pseudomorphic InGaAs channels, 30 MHz to 23.6 GHz prescaler operation is demonstrated at room temperature. The performance improves at 0 degrees C, while at 70 degrees C the upper frequency typically drops by 2 GHz. Correct high-speed pulse-mode operation requires (1) presetting which does not degrade the performance and (2) suppression of self-oscillation during quiet periods between pulse bursts. The circuit design provides for both, and pulse-mode operation without ringing, or pulse loss, at 22.4 GHz (present testing limit) has been confirmed. >

An analytical model for oscillator noise resulting from active device LF noise is presented. We apply it to a number of GaAs MESFET oscillators finding good quantitative agreement, and demonstrating several ways of reducing the phase noise. We show evidence that after having reduced the effect of the normally dominant device LF noise source, a residual LF noise source starts to dominate the phase noise. The best phase noise result for the 5GHz oscillators is S/sub phi/(1kHz) = -75dB/Hz.

We report the growth of high-quality InP/GaAsSb heterojunction bipolar transistors (HBTs) for high-frequency applications by metalorganic vapor phase epitaxy (MOVPE) and gas-source molecular beam epitaxy (GSMBE) using carbon as a base dopant. Hole concentrations above 10/sup 20/ cm/sup -3/ are achieved in a carbon-doped GaAsSb base layer. We measure type I and type II luminescence from InP/GaAsSb/InAlAs and GaAsSb/InP superlattices to evaluate quickly the HBT's GaAsSb base layer and collector-base and base-emitter heterojunction quality. The HBTs exhibit excellent DC characteristics and a current gain cutoff frequency over 210 GHz.

By utilizing a novel ZEP/PMGI/ZEP trilayer resist process, GaInAs/AlInAs T‐gate modulation‐doped field effect transistors on InP with 0.1 μm gate lengths have been demonstrated. The trilayer resist requires only a single exposure. An overhang structure for liftoff, with a 0.1 μm footprint, is created by a sequence of infinitely selective developments for each layer. Linewidths as narrow as 65 nm have been obtained. Devices with a maximum current of 860 mA/mm, extrinsic transconductances of 658 mS/mm, and a current‐gain‐cutoff frequency ft of as high as 203 GHz have been fabricated. Yields as high as 96% and a threshold voltage uniformity of 34 mV (1 sigma) have been achieved on a 2 in. wafer.

We have modeled numerically the redistribution by diffusion and drift of impurities during epitaxial growth of semiconductors. We use a Crank-Nicholson scheme with dynamically adjusted time increment. The coupling between the redistribution of the charged impurities and the electric field is accounted for by solving the nonlinear Shockley-Poisson equation for an arbitrary doping profile by means of a quasi-linearization scheme. The combination of large gradients and a moving boundary necessitates a dynamically adjusted nonuniform mesh in the finite difference schemes. Except for some occasionally occurring spurious ripples, which are accounted for by stability arguments, the results are physically real and can explain some experimentally observed features[1].

The correlation of the capacitance-voltage characteristics of fat MODFETs (FATFETs) to the current-voltage characteristics of FATFETs and the pulse-doped MODFET is reported. The measured gate capacitance is fitted using a noniterative numerical algorithm. The effective doping concentration of the GaAs buffer region and AlGaAs pulse-doped region is extracted along with the dependence of two-dimensional electron gas concentration upon the applied gate voltage. An excellent agreement between the threshold voltages calculated from the measured gate capacitance relation and the I-V characteristics is obtained for FATFETs. The correlation of the average threshold voltages of MODFETs and FATFETs appears to be technology-dependent. A good correlation of the average threshold voltage of MODFETs and FATFETs is observed on a wafer featuring Schottky gate diodes with good ideality coefficients. The comparison of the present semianalytic I-V model with a hydrodynamic model demonstrates that velocity overshoot above the GaAs peak stationary velocity does not appreciably improve the saturation transconductance. The two-dimensional field effects associated with the 2DEG channel width are also shown to bring a minimal contribution to the drain conductance of MODFETs. >

We have developed a model of Cr in GaAs which is consistent with a large body of experimental data. It relies or recent spectroscopic models and on our interpretation of redistribution and electrical data, all of which indicate the existence of Cr complexes. The existence of rapidly diffusing interstitial Cr donors is assumed and justified. The model offers a unified picture of the effects of implantation on the Cr profile. It contains mechanisms for compensation and redistribution, which offer an explanation of the semi-insulating properties of Cr doped GaAs and of the two apparently incompatible classes of diffusion and anneal data. The redistribution depends on how the Cr was incorporated and on the vacancy concentration profiles. A study of representatives of the two classes of redistribution data allows us to estimate a lower limit of interstitial Cr diffusion constant and of the vacancy diffusion lengths in GaAs.

The distribution of impurities incorporated in epitaxial layers during their growth is determined by diffusion due to concentration gradients and by drift in the built-in electric field. This problem has been previously treated in the approximation that the impurities reach their equilibrium distribution during growth. We have extended this calculation to treat impurity drift and diffusion under non-equilibrium conditions, a situation much more characteristic of most realistic growth condi-tions. In the new calculation, the solution of the Shockley-Poisson problem is exact and the boundary con-dition at the growth interface is an approximation based on the electrostatics of surface states. The new calcu-lation also permits consideration of outdiffusion from the substrate, a phenomenon of technological significance. It is also capable of modeling variations of source im-purity concentration and growth rate during epitaxial growth. Calculations modeling n-type GaAs epitaxy of practical interest are presented.

Modulation-doped field-effect transistors (MODFETs) exhibit transient responses that contain a variety of time constants. The strongest transients observed in the microsecond range are known to be caused by the DX centers. MODFETs also suffer a transient that arises from a source different from that of the DX centers. Preliminary measured characteristics of the nanosecond transient are presented, its effects on circuit performance are described, and its possible origin is inferred. >

The origin of low frequency noise in GaAs MESFETs was experimentally investigated. Traps in a depletion region of the MESFET were found to be primarily responsible for the low frequency noise. The observed dependence of the low frequency noise on the gate length supports this conclusion.