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Nano scale devices with improved performance than the conventional CMOS devices is of great need in recent days. The paper investigates the performance of 10 nm Trigate FinFET structure with high k dielectric spacer on either side of the channel in the underlap region. The proposed structure increases the On-Off ratio (ION/ IOFF) of drain current by order of 106 and also improves the subthreshold swing (SS). Further, it enhances the transconductance (gm) at the low gate voltage, raises the output conductance (gd) and intrinsic gain (gm/gd) proving that the device provides efficient analog performance suitable for RF applications.

The performance of InAs/GaSb core-shell nanowire TFET is systematically investigated for the effects of intrinsic device parameters such as channel doping, shell thickness, spacer length and source offset. Device ON-current (ION) was chosen as the key figure of merit. It is found that ION improves due to improved electrostatic control achieved by the TFET with optimum shell diameter. The maximum ION obtained for a shell thickness of 2 nm was 33.65 μA/μm and a Subthreshold Swing (SS) of 12.9 mV/decade with an ION/IOFF ratio of 1.49 × 108 for our device. Device ION can be further improved by adding an optimum spacer at the source-channel junction. It was also found that device ON-current is almost constant and does not get much affected by having a larger shell offset.

In this study, the structure of efficient recessed gate Metal Insulator Semiconductor High Electron Mobility Transistor with Quaternary Barrier materials of Al0.42ln0.03Ga0.55N was simulated and presented. The device with heterostructure of Al0.42ln0.03Ga0.55N/UID-AIN/GaN/GaN and thickness of 5 nm/10 nm/40 nm/10 μm on SiC substrate shows normally-OFF characteristics. The effect of high~k dielectrics of HfAlxOx and the quaternary barrier on the electrical performance of the device was analyzed and compared with the conventional AlGaN/GaN heterostructure. We found that the charge optimization concept of the polarization induced charges of the device 2DEG in the channel was due to the combination of the Quaternary Barrier of Al0.42ln0.03Ga0.55N and the high~k dielectrics of HfAlxOx. Furthermore, the two field plates used which are having a length of plate at the drain (LGFP) of 1.8 μm and field plate at the source (LGPS) 0.5 μm effectively spread the electric field lines with the drain and showed a significant improvement in the electrical properties of the device and achieved a maximum drain current of 710 mA/mmV, low transconductance (gm) of 0.158 Smm−1 and high breakdown voltage of 570 V. In comparison to the conventional AlGaN/GaN MIS-HEMTs of similar design, the result of this Quaternary Barrier Metal Insulator Semiconductor High Electron Mobility Transistor (QB-MIS-HEMTs) exhibited a better interface property, remarkable suppression of leakage current, and excellent breakdown voltage which are important for power switching applications.

This paper investigates the effect of counter doping in an n-Tunneling Field Effect Transistor(nTFET). Effect of various pocket lengths between the source and the channel was investigated. A double gate structure with a 2 nm counter doped pocket provides higher rate of band-to-band tunneling and better on current, thereby increasing the device performance. Steep Subthreshold Swing (SS) of around 23 mV/dec was obtained due to larger band bending at a low operating voltage of 0.5 V. The low leakage current greatly reduces power consumption. The degree of depletion in pocket with smaller dimensions enhances device performance by achieving good electrical characteristics in both above and below threshold regimes. Increase in pocket length degrades the device performance thus affecting the subthreshold swing.

A comprehensive investigation with the help of 3D device simulation, we demonstrate the impact of fringing field on shell radius of InAs-GaSb core–shell nanowire n-channel tunnel field effect transistor (TFET) in this paper. Increase in shell radius intensifies the magnitude of fringing electric field towards shell region. This results in generation of depletion zone in the shell near the gate edge affects the device performance metrics such as on current and threshold voltage. It is demonstrated that by appropriate gate engineering the influence of fringing electric field can be circumvent. High-k spacer dielectric at the gate underlap shows improvement in device performance metrics such as on current with sub 2.3 k B T q subthreshold swing. An investigation of the effect of drain voltage on the device characteristics exhibits the privation of tunneling resistance limited region. Furthermore, the output characteristics for such an architecture bear a resemblance to long channel MOSFET (metal oxide semiconductor field effect transistor).

The electron transport properties of an electrostatic gated single molecular transistor are investigated by using self-consistent semi-empirical method. The charge transport characteristics of the molecular device are analysed through the current-voltage I SD−V SD characteristics transmission characteristics T (E), and molecular projected self-consistent Hamiltonian states analysis. It is revealed that the gate bias V G can effectively tune the transport properties to greater extent. The mechanisms governing the gate bias tuned transport properties in this device were discussed. The proposed device also exhibits gate modulated negative differential resistance feature, which is exploited in realising basic logic gates. Thus, by using source-drain resistance R as a function of V G, the application of using gated thiophene based molecular device to realise a set of five basic logic gates at particular V SD is shown. The significant feature of the proposed device is the possibility of realising different logic gates with just one molecular transistor using computationally inexpensive semi-empirical method.

The impact of EOT (Equivalent Oxide Thickness) scaling, diameter scaling, and interface traps on the performance of gated InAs/Si Hetero pTFET (Tunneling field effect transistor) is investigated. EOT scaling improves SS (SubthresholdSwing) below the thermal limit and on current moderately. Diameter scaling decreases on current and marginally improves SS. The simulation study validates that the transfer characteristics of pTFET in subthreshold region are completely dominated by thermionic emission of holes and TAT (Trap Assisted Tunneling). This in turn blocks SS to attain

In this paper, Al0.23Ga0.77N/GaN/Al0.05Ga0.95N Double Heterostructure-High Electron Mobility Transistor targeting a low loss and high power efficient boost converter circuit was simulated using a thin P+In0.2Ga0.8N cap under the gate. The charge balancing concept of the polarization induced field of the device was due to the Mg-doped P+In0.2Ga0.8N which shows normally-off characteristics. The high positive threshold voltage VT shift achieved with the device was correlated with the obtained dynamic RON of the device. This dynamic RON was characterized 19 μ s immediately after the device was turned-on and goes up to a maximum of 550 V. Furthermore, this Al0.23Ga0.77N/GaN/Al0.05Ga0.95N demonstrates low dynamic RON of ~6% with increment of efficiency of up to 40% when measured in the booster converter circuit. For power switching applications, the result of this P+In0.2Ga0.8N cap having a back-barrier/buffer of AlGaN achieved a dynamic RON performance with excellent breakdown Voltage VBR.OFF and much lower OFF-state gate/drain leakage as compared to the conventional GaN buffer structures.