Search

This paper describes the structure, fabrication and detailed characterization of a polycrystalline silicon passive microvalve. The microvalves were fabricated utilizing micromachining techniques, and automated measurement systems were developed for device characterization. The valves were successfully characterized to determine the effect of dimensions on fluid flow rate and valve deflection. Methanol, deionized water and nitrogen were used for fluid flow tests, and nitrogen gas was used in the deflection measurements. The ratio of reverse to forward flow rates of methanol was found to be less than 3% at a pressure of 11 kPa. The measured data are in good agreement with a first-order model for the device taking into account applied pressure, valve plate deflection and the resistance of the inlet hole. Using nitrogen gas, analysis of the device was extended to measure the valve plate deflection as a function of inlet pressure. Valve plate deflections of up to 15.3 μm were recorded at 31 kPa. The nitrogen gas flow characteristics differ significantly from the liquid flow characteristics due to the compressible nature of the fluid, but agree well with the theoretical flow for gases.

Silicon-on-insulator (SOI) structures comprised of fully dielectrically isolated device wells have been fabricated, utilizing a trench-before-bond process to create polish stops. The SOI layers have thicknesses between 1.5 and 3.0 μm with uniformities of ± 5% across a 500 μm device well, which would not be achievable with grind and polish techniques only. The SOI layer thickness was defined by the depth of isolation trenches, formed prior to bonding, which acted as the final SOI polish stops. The prebond planarization process is very dependent on polish conditions used. It was found that opting for a polishing slurry with a lower pH value allowed the planarization of polysilicon layers. The polish process resulted in refill layers that could be bonded without pattern-related voids. A similar polishing process also displayed minimal dishing in the final SOI device wells, as the variability of the polishing process is limited by the polish stops. The trench-before-bond process minimizes the risk of oxidation-induced defects, arising from SOI isolation trenches, as these are refilled prior to bonding. It also offers a cheaper alternative to epitaxial growth on SIMOX substrates as a means of obtaining layers within this thickness range.

Using the Otto (prism-air gap-sample) configuration p-polarized light of wavelength 632·8 nm has been coupled with greater than 80% efficiency to surface plasmons on the aluminium electrode of silicon-silicon dioxide-aluminium structures. The results show that if the average power per unit area dissipated on the metal film exceeds approximately 1 mW mm−2, then the coupling gap and thus the characteristics of the surface plasmon resonance are noticeably altered. In modelling the optical response of such systems the inclusion of both a non-uniform air coupling gap and a thin cermet layer at the aluminium surface may be necessary.

SOI technology with trench isolation has increased packing density of bipolar integrated circuits and improved their performance through a significant reduction in parasitic capacitance. A further improvement in performance could be obtained if the collector series resistance was reduced. This paper examines the technology for the incorporation of a metal silicide layer between the silicon layer and the buried oxide. These silicon on silicide on insulator (S2OI) layers are characterised using MOS and p-n junction test structures and shown to be of device quality. Examples are presented from the literature of possible applications for S2OI substrates. A post bond polish stop process suitable for producing nanometre thick S2OI layers for research device structures is outlined. Finally, a new process for producing complementary bipolar circuits using S2OI substrates is proposed.

A technique for enhancing the conductivity of polysilicon interconnects by self‐aligned layers of platinum has been developed. A sheet resistance of approximately 1 Ω/⧠ was achieved for an interconnect height of 270 nm. Very thin layers of platinum have also been used to provide self‐alignment of other metals such as nickel, titanium, and aluminum. Nickel and titanium required prolonged ultrasonic processing to achieve self‐alignment to the polysilicon, as their specific stiffness coefficients were less favorable than that of platinum. Aluminum self‐alignment was only achieved after overlaying with films of nickel and platinum, and subsequently removing the latter layers by dissolving the nickel in fuming nitric acid. Polysilicon interconnects enhanced with a layer of self‐aligned aluminum yielded a sheet resistance of 1.2 Ω/⧠ for a total interconnect height of 120 nm. Metal‐oxide semiconductor (MOS) transistors and ring oscillators manufactured with metal enhanced interconnects showed no degradation effe...