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Your search keyword '"Gwendal Le Fol"' showing total 6 results
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6 results on '"Gwendal Le Fol"'

1. Changes to the structure and function of an albacore fishery reveal shifting social‐ecological realities for Pacific Northwest fishermen

Author

Barbara A. Muhling, Stephen S. Stohs, Elena M. Finkbeiner, Elliott L. Hazen, Desiree Tommasi, Stephanie Brodie, Mary C. Fisher, Gwendal Le Fol, Timothy H. Frawley, and Michael G. Jacox

Subjects
Fishery, Geography, biology, Ecology, Albacore, Management, Monitoring, Policy and Law, Aquatic Science, Oceanography, biology.organism_classification, Ecology, Evolution, Behavior and Systematics, Structure and function
Published
2020
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2. Projecting climate change impacts from physics to fisheries: A view from three California Current fisheries

Author

James A. Smith, Mercedes Pozo Buil, Barbara Muhling, Desiree Tommasi, Stephanie Brodie, Timothy H. Frawley, Jerome Fiechter, Stefan Koenigstein, Amber Himes-Cornell, Michael A. Alexander, Steven J. Bograd, Nathalí Cordero Quirós, Larry B. Crowder, Enrique Curchitser, Stephanie J. Green, Natasha A. Hardy, Alan C. Haynie, Elliott L. Hazen, Kirstin Holsman, Gwendal Le Fol, Nerea Lezama-Ochoa, Ryan R. Rykaczewski, Charles A. Stock, Stephen Stohs, Jonathan Sweeney, Heather Welch, and Michael G. Jacox

Subjects
Geology, Aquatic Science
Published
2023
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5. MOVIE: a hardware building block for software-only real-time video processing

Author

Ronan Barzic, François Charot, Gwendal Le Fol, Christian Bouville, Pascal Lemonnier, and Charles Wagner

Subjects
Computer science, business.industry, High-level programming language, Block (programming), Computer programming, Array data structure, Local variable, Array processing, Video processing, SIMD, business, Computer hardware
Abstract

The goal of the MOVIE VLSI chip is to facilitate the development of software-only solutions for real time video processing applications. This chip can be seen as a building block for SIMD arrays of processing elements and its architecture has been designed so as to facilitate high level language programming. The basic architecture building block associates a sub-array of computational processors with a I/O processor. A module can be seen as a small linear, systolic-like array of processing elements, connected at each end to the I/O processor. The module can communicate with its two nearest neighbors via two communication ports. The chip architecture also includes three 16-bit video ports. One important aspect in the programming environment is the C-stolic programming language. C-stolic is a C-like language augmented with parallel constructs which allow to differentiate between the array controller variables (scalar variables) and the local variables in the array structure (systolic variables). A statement operating on systolic variables implies a simultaneous execution on all the cells of the structure. Implementation examples of MOVIE-based architectures dealing with video compression algorithms are given.

Published
1996
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6. SALTO : System for Assembly-Language Transformation and Optimization

Author

Erven Rohou, François Bodin, André Seznec, Gwendal Le Fol, François Charot, Frédéric Raimbault, Compilation, parallel architectures and system (CAPS), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria), Parallel VLSI Architectures (API), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-INRIA Rennes, Université de Bretagne Sud (UBS), INRIA, Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Inria Rennes – Bretagne Atlantique, and Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-INRIA Rennes

Subjects
USER INTERFACE, COMPILATION PROCESS, ASSEMBLY LANGUAGE, [INFO.INFO-OH]Computer Science [cs]/Other [cs.OH], EMBEDDED SYSTEMS, OBJECT ORIENTED, OPTIMIZATION, RESERVATION TABLES
Abstract

On critical applications, particularly embedded systems, the performance tuning requires multiple passes. SALTO (System for Assembly Language Transformation and Optimization) is a retargetable framework for developing all the spectrum of tools that are needed for performance tuning on low-level codes (assembly-languages) on uniprocessors. SALTO enables the building of profiling, tracing and optimization tools. The user is responsible for giving a machine description of the target architecture, which includes instruction-set of the processor, precise hardware configuration and reservation-tables for all instructions, but high-level functions are provided to him for writing any tool corresponding to his needs. Moreover SALTO will be a part of a global solution for manipulating assembly-code to implement low-level code restructuration as well as to provide a high-level code restructurer with useful information collected from the assembler code and from instruction profiling. SALTO has been tested on Intel platforms running Linux (i486) and Solaris (PentiumPro) and on a Sparcstation running SunOs 4.1. A machine description for the Sparc v7 architecture is currently available. Two examples, a basic block instrumentation and a local reordering optimization, are given in the paper as illustration.

Published
1996

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