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Band-to-band tunneling (BTBT) [1] and trap-assisted tunneling (TAT) [2] have been observed in the forward operation base current of SiGe HBTs [3], due to increasing emitter-base junction doping and decreasing bandgap from high Ge mole fraction. At present, a compact model for the BTBT base current in forward operation does not exist. The reverse bias BTBT current is modeled in Mextram for both emitter-base and collector-base junctions. A compact model of the forward TAT base current was developed by our group for wide temperature range operation [4]. In this work, we present a new compact model of BTBT and further develop the TAT compact model of [4] for commercial temperature range application, and demonstrate their effectiveness on SiGe HBTs with around 250 GHz peak fT and fmax. Fig. 1 shows measured IB-VBE characteristics at several temperatures, together with simulation using the latest version of Mextram, 505.3. VCB=0V. At moderate VBE, the IB-VBE slope starts to decrease, similar to high injection effect in diodes, when we know high injection has not occurred as IC-VBE slope remains its low injection value (not shown). Such behavior cannot be modeled with standard base current models. A newly developed neutral-base-recombination (NBR) model introduced in 505.3 is used to fit such high-injection like IB-VBE behavior [5]. In this work we focus on the low VBE regions. At VBEB first increases, then decreases, exhibiting a negative differential resistance, which is due to BTBT [3]. This BTBT region shows very weak temperature dependence. IB then slowly increases, with a large non-ideality factor of 3.78, which we believe is due to TAT [2] [3] [4]. Note that this should not be confused with the depletion-region recombination current, called IB2 in Mextram [5], with an ideality factor close to 2. The corresponding saturation current in this “TAT” region shows a temperature dependence much weaker than what one expects from the depletion region recombination current as well. Our BTBT model is based on the approach of Esaki [1] and Karlovsky [6], and has a simple functional form: IB,BTBT = kBTBTVBE,btbt(VBE,btbt – VBTBT)2, KBTBT and VBTBT are model parameters that can be extracted from the IB peak position and slope of IB-VBE followed by optimization. VBTBT has a physical meaning of VBTBT =[(Efn-Ec)|n-side+(Ev-Efp)|p-side]/q, with all symbols having their usual meanings in PN junctions. VBE,btbt is a smoothly limited version of VBE for modeling BTBT. When VBEBE is smoothly limited to 0, i.e. VBE,btbt->0, so that it does not interfere with the existing reverse bias BTBT model. When 0BE< VBTBT, VBE,btbt is essentially equal to VBE by design except at the boundaries. When VBE>VBTBT, VBE is smoothly limited to VBTBT, so that the BTBT current decays to zero, as there will be no aligned available states for BTBT. We observe that the BTBT current is insensitive to temperature, consistent with [3], and find that no temperature scaling is necessary for modeling the BTBT current. The TAT current is modeled as ITAT = ISTAT(exp(VBE,tat/VTUN)-1), with VTUN and ISTAT as model parameters [4]. VBE,tat is approximately VBE when VBE>0, and smoothly becomes zero when VBESTAT scales with temperature T according to ISTAT,T=ISTAT(T/Tref)1/2exp(kTAT(T-Tref)), where Tref is the reference temperature, and kTAT is a temperature scaling model parameter. VTUN is temperature independent. Fig. 2 shows the 25°C IB-VBE modeling result at low VBE using a linear current scale, to better illustrate the behavior of all IB components at low VBE. Fig. 3 shows a full range view on a logarithmic scale. Fig. 4 shows the modeling results at all four temperatures, with the insert showing the low bias details. Overall the proposed BTBT and TAT models do a good job fitting the forward operation IB-VBE characteristics, with an easy to use formulation, and a small number of model parameters, 2 for BTBT and 3 for TAT. References [1] L. Esaki, Phys. Rev., vol. 109, pp. 604–605, Jan. 1958. [2] A. G. Chynoweth et al., Phys. Rev., vol. 121, pp.684-694, Feb. 1961. [3] D. Lagarde et al., IEEE Electron Device Letters, vol. 27, no. 4, pp. 275-277, April 2006. [4] Z. Xu et al., ECS Transactions, vol. 33, no. 6, pp. 301-310, 2010. [5] G. Niu et al., The Mextram Bipolar Transistor Model Version 505.3.0, 2022. [6] J. Karlovsky, Phys. Rev., vol. 127, pp. 419–419, July 1962. Figure 1

This paper presents several recent advances in compact modeling of avalanche multiplication in Mextram 505, an industry standard transistor model, including both new model features and improved model implementations. Implications of these improvements on circuit simulation are illustrated using RF SiGe HBTs. Feature wise, Mextram 505 adds a new physics-based model of the avalanche multiplication factor that accounts for the complex evolution of the epi-layer electric field at high current density, which can be activated with swavl=3. At a given collector-base bias VCB, the avalanche factor Gem is constant at low collector current density JC, starts to decrease when mobile electron density becomes comparable to epi-layer doping density due to charge compensation, and ultimately increases again when the base pushes out, and the electrical CB junction shifts to the epi-layer/buried layer interface. A parameter exavl can be used to turn on/off the rise of Gem at very high JC. An example of fitting IB versus IE for a common-base RF SiGe HBT at a fixed VCB=3V is given in Fig. 1. The measured base current is calculated from the difference of measured IE and IC, and hence shows some measurement noise. At low IE, Gem is constant, IB is linearly proportional to IE, with exavl=0, only the decrease of Gem with increasing JC is modeled, the IB bends upward at 0.05 A. With exavl=1, the rise of Gem at high JC is modeled, allowing the fitting of the downward bending of IB above 0.1 A. We will also discuss implications of such complex Gem behavior for RF linearity, particularly on the modeling of linearity sweet spots, i.e. biasing currents and voltages at which linearity peaks. Implementation wise, Mextram 505 uses the main current In as the initiating current in calculating the avalanche current Iavl, i.e. Iavl = In*Gem, as opposed to using the epi-layer current Ic1c2, i.e. Iavl = Ic1c2*Gem in Mextram 504. While for DC I-V, one can always use slightly different Gem model parameters to achieve the same degree of fitting, we found that the Mextram 504 approach can lead to unphysically high avalanche noise in voltage-controlled oscillator (VCO) circuits in some cases. Users should inspect the waveforms of Iavl as well as In to determine if this problem exists. The root problem is that the epi-layer current Ic1c2 also includes the CB junction capacitive charge current, which should not experience avalanche as the corresponding electron motion occurs outside the space charge region. While the Iavl error introduced has a small absolute value, the noise it introduces is often significant, and significantly increases oscillator phase noise. At the device level, this unphysical avalanche of capacitive charge current comes into play during modeling of the CB depletion capacitance, CCB, which is often extracted from off state y-parameter. Fig. 2 compares the CCB vs VCB simulated using In (505) and Ic1c2 (504) as avalanche initiating current, together with the CCB from measurement. The Gem value is shown on the right y-axis. When Gem approaches 1, the simulated CCB using Iavl = Ic1c2*Gem increases sharply, and becomes negative when Gem>1, a unphysical result users of Mextram 504 need to be aware of for high Gem biases. Using Iavl = In*Gem, as is in Mextram 505, the simulated CCB remains physical when Gem is high. An analytical model of such discrepancy has been developed using small signal frequency domain analysis and will be presented. In Mextram 504 and earlier versions of Mextram 505, Gem is limited to be less than 1 and then further limited through elegant considerations that ensure the collector current increases monotonically with the external VBE. Such limiting, however, cannot possibly work for the dynamic charge current which is the issue in the off-state CCB example as well as the VCO example above, due to how model equations are implemented in circuit simulators. One side effect of this Gem limiting is that avalanche induced runaway cannot be modeled for investigating safe operating area (SOA). A switch swgemlim is introduced in Mextram 505.3 to allow the users to turn off Gem limiting for such modeling, as shown in Fig. 3. The new avalanche model in Mextram 505 also enhances its ability to accurately predict the SOA boundary due to electrothermal runaway from the combined effects of avalanche and self-heating. Figure 1

An important aspect of compact modeling for RF application is to accurately model the biasing current at which transistor linearity is maximized, i.e. where the third order intercept point, IP3, peaks. We have shown recently that for common-emitter SiGe HBTs, Mextram 504.12 has problem modeling the IP3 peak behavior at high injection [1]. We have further developed a couple of new modeling options in Mextram 505 [2] for CB junction depletion capacitance intended to improve IP3 peak modeling [1]. However, the detailed mechanisms of how these improved CB junction depletion capacitance models translate into IP3 peak modeling improvement remains unclear and require further investigation. For instance, the collector current, which is the output current, consists of the transistor main current In that flows from the collector to the emitter, and the CB junction capacitance discharging current that flows from the collector to the base. With the change of CB junction depletion capacitance model, which distortion current is dominant, In or the CB discharging current, in determining IP3 peak? Through detailed analysis of the harmonic components of the individual branch currents at the collector node of the Mextram large signal equivalent circuit, we find that the In distortion current dominates in determining IP3 peak behavior. The next logic question is if the In distortion current improvement with the Mextram 505 CB depletion capacitance models is directly due to the normalized base hole charge term, q1I in Mextram terminology, that goes directly into the In expression, or indirectly due to propagation of the CB discharging current induced distortion to IN, through circuit interactions. We will show that it is the later rather than the former with carefully designed custom Verilog-A codes of Mextram, by using separate CB depletion capacitance models in the main current equation formulation and the CB depletion charge equations. Changing the CB depletion capacitance model used in the main current equation leads to no visible changes in IP3, while changing the CB depletion capacitance model used in the CB depletion charge equation leads to obvious changes in third order output current and hence IP3. This proves that the observed third order distortion current improvement in In responsible for the improved IP3 peak modeling in Mextram 505 fundamentally results from the CB depletion charge term, despite the small values of third order distortion in the CB depletion charge current itself. We will then further examine how reducing the CB junction depletion capacitance might affect IP3 and how the partition between extrinsic and intrinsic CB junction capacitance affects IP3 peak behavior. Interestingly, simply making all CB depletion capacitance extrinsic gets rid of the IP3 peak modeling problem in Mextram 504, implying that the high injection related increase of the intrinsic CB junction depletion charge control voltage Vjunc and its related smooth limiting parameter Vch are the root problems. A reduction of CB depletion capacitance, intrinsic or extrinsic, is found to be beneficial for IP3 peak improvement. [1] G. Niu, H. Zhang, Y. Li, X. Ding, M. Willemsen, and A. Scholten, “Physics and Compact Modeling of SiGe HBT Linearity Using Mextram,” ECS Transactions, 86 (7), pp. 145-154, 2018. [2] G. Niu, R. van der Toorn, J. C. J. Paasschens, W. J. Kloosterman, The Mextram Bipolar Transistor Model, 505.10, Model Definition Document, Auburn University, 2019.

This paper investigates the RF intermodulation characteristics of transistors from a 14-nm RF FinFET technology using experimental measurements, circuit simulation with Berkeley short-channel IGFET model-common multi-gate (BSIM-CMG), and Volterra series. Linearity sweet spots with respect to gate voltage and RF power, as well as its drain voltage dependence, are examined. Key BSIM-CMG model parameters required for simultaneous fitting of dc I–V , S-parameters, and intermodulation distortion are identified and demonstrated. Volterra series analysis shows that distortion resulting from ${V}_{\textsf {DS}}$ derivatives of ${I}_{\textsf {DS}}$ dominates at most biases. A minimum third-order intercept gate voltage ${V}_{\textsf {GS,IP3}}$ of 0.5 V is observed, compared with 0.7 V in a 28-nm high- ${k}$ metal-gate planar device.

We review linearity of SiGe HBTs, from physics to RF measurements using X-parameter capable NVNA, to compact modeling using Mextram 505, an industry standard model. New models of high injection depletion capacitance and avalanche enable accurate linearity sweet spot modeling. Source distortion and port mismatches can be accounted for using X-parameters to significantly improve measurement accuracy, which also greatly simplifies circuit setup in modeling.

This paper experimentally extracts the extrinsic and intrinsic thermal noise γ factors in a 14-nm FinFET technology. The intrinsic γ in saturation operation is found to be close to 1 for the minimum L (16nm) transistors, which is surprisingly low compared to the long channel limit of 2/3. We attribute this low noise factor to the excellent gate control of these FinFETs that makes the transistor exhibit relatively long channel thermal noise behavior at minimum gate length.

This paper compares RF characteristics and compact modeling of PMOS and NMOS in a 14-nm FinFET technology. DC I-V as well as its higher order derivatives, y-parameters, and two-tone intermodulation are measured and modeled. Similarities and differences between NMOS and PMOS are highlighted.

This paper investigates RF noise in a 28-nm replacement metal gate RF CMOS technology. The gate resistance is shown to be limited by interfacial resistance in metal gate stack. Intrinsic noise factor $\gamma _{\mathrm{ gd0}}^{\mathrm{ int}} ={S}_{\mathrm{ id}}^{\mathrm{ int}}/\text{4kTg}_{\mathrm{ d0}}$ and shot noise suppression factor ${k}_{s}^{\mathrm{ int}} = {S}_{\mathrm{ id}}^{\mathrm{ int}}/\text{2qI}_{\mathrm{ DS}}$ are extracted. $\text{g}_{\mathrm{ d0}}$ from S-parameters is shown to be more accurate than from dc ${I}$ – ${V}$ . $\gamma _{\mathrm{ gd0}}^{\mathrm{ int}}$ remains less than 2, despite a large increase from 90-nm gate length, as well as a much stronger increase with ${V}_{\mathrm{ DS}}$ . ${k}_{s}^{\mathrm{ int}}$ shows a decrease on ${V}_{\mathrm{ GS}}$ and a weak increase on ${V}_{\mathrm{ DS}}$ . Of all four noise parameters, noise resistance plays the most significant role in intrinsic drain current noise extraction. Extrinsic and intrinsic noise resistance can be modeled by simple expressions.

This paper demonstrates that collector current ( $I_{C}$ ), dc current gain ( $\beta $ ), cutoff frequency ( $f_{T}$ ), and maximum oscillation frequency ( $f_{\max }$ ) of bipolar transistors (BJTs) can be improved by uniaxial stress. A unified modeling approach that includes a piezoresistive model for changes in mobility and a deformation potential model for changes in intrinsic carrier concentration was used to analyze the stress effects. This approach provides clear insight into the dominant effects of stress on BJT parameters. Experimental results of uniaxial in-plane normal stress are compared with simulation results. Our analysis reveals that for a vertical npn, substantial enhancement in $I_{C}$ , $\beta $ , $f_{T}$ and $f_{\max }$ can be achieved using a uniaxial in-plane compressive or out-of-plane tensile stress. In a vertical pnp, considerable improvement in $I_{C}$ can be achieved with an in-plane or out-of-plane compressive stress while the changes in $\beta $ , $f_{T}$ , and $f_{\max }$ are minimal. These results show that stress analysis/prediction for different current-stress orientations can be performed with this model and the outcome can be used as a guide for strain engineering in BJTs.

A new approach to modeling of thermal coupling based on current-controlled current sources is developed. The approach is compatible with existing compact models, simple to implement, and does not require any additional circuit nodes. A Verilog-A implementation is presented, along with an SiGe heterojunction bipolar transistor example.

Summary This paper investigates modeling of silicon-germanium heterojunction bipolar transistor noise parameters and impedance-matched Low-Noise Amplifiers (LNAs) intended for operation across a wide temperature range (from 93 to 393 K). In general, noise performance improves with cooling until about 150 K, then degrades some because of carrier freeze-out. With a temperature independent bias current, an LNA designed for 300 K operation shows acceptable performance from 93 to 393 K, albeit with some degradation of linearity below 120 K. Copyright © 2015 John Wiley & Sons, Ltd.

This paper presents analytical models of SiGe HBT and low-noise amplifier (LNA) noise parameters accounting for high-frequency noise correlation. The models are verified using measurement data and circuit simulation. The impact of noise correlation is shown to be a strong function of base resistance \(r_{\rm b}\) and emitter resistance \(r_{\rm e}\) , which act as both noise sources and resistance. Correlation and roles of \(r_{\rm b}\) and \(r_{\rm e}\) as resistance have opposite effects on minimum noise figure \(N\!F_{\rm min}\) , which explains why a widely used \(N\!F_{\rm min}\) model that neglects correlation and roles of \(r_{\rm b}\) and \(r_{\rm e}\) as resistance sometimes agreed with measurements. The agreement, however, does not hold for noise matching source resistance \(R_{\rm opt}\) , an important parameter for LNAs. With correlation, noise matching condition is better met for impedance matched LNAs.

This paper examines the impact of quasi-ballistic transport (QBT) on bipolar transistor (BJT) intrinsic terminal current noise by analytically solving the general 3-D minority carrier noise transport equation using Hansen's nonhomogenous boundary conditions with extensions to include injection noise. Transistor noises are further expressed in Y-parameters, as was done in the widely used van Vliet model, with extra corrections accounting for QBT. For 10-nm base width of BJTs without base built-in field, while QBT is significant in affecting IC, Sic is shown to be less than but close to the classic 2qIC.

A new approach to implementing correlated high-frequency noise in bipolar junction transistor (BJT) large-signal compact models is developed by placing an RC -delayed noise current between the base and collector nodes. The approach reproduces the two stages of noise transport in a BJT, i.e., noise generation in the base and emitter and transportation through the collector-base junction space-charge region (CB SCR). The frequency dependence of the intrinsic noise sources due to the CB SCR is fully described with an accuracy value up to the second order of ω. As an example, the negative frequency dependence of Sic is correctly described for the first time. The approach is applicable to any large-signal compact model, and it is demonstrated using measurement data in both InGaP/GaAs heterojunction bipolar transistors (HBTs) and SiGe HBTs.

We present a rigorous electrical and optical analysis of a highly scaled, graded-base, SiGe heterojunction bipolar transistor (HBT) electrooptic (EO) modulator. In this study, we propose a 2-D electrical model and a 3-D optical model for a graded-base SiGe HBT structure that is capable of operating at a data bit rate of 250 Gbit/s or higher. In this structure, apart from a polysilicon/low doped emitter ( width = 90 nm) and a strained SiGe graded base ( depth = 8.5 nm), a selectively implanted collector (SIC) (depth = 26 nm) is introduced. Furthermore, at a base-emitter swing of 0 to 1.0 V, this model predicts a rise time of 3.48 ps and a fall time of 0.55 ps. Optical simulations predict a π phase shift length (Lπ) of 204 μm, with an extinction ratio of 13.2 dB at a wavelength of 1.55 μm.

Comprehensive 3-D mixed-mode simulations, including accurate modeling of parasitic elements present in the experimental setup, resulted in close agreement between simulated and experimentally-measured heavy-ion-induced transients in first-generation SiGe HBTs. We have identified the key factors affecting previous simulations and observed experimental differences. The approach employed is also applicable to other submicron, high-speed technologies. Furthermore, we present a plausible answer to the previously unexplained issue of higher collector currents in single-transistor SiGe HBT single-event transients under positive collector bias. The new observations and conclusions facilitate improved understanding and potential mitigation options.

This paper models the input non-quasi-static (NQS) effect of bipolar transistors using charge partitioning. The input NQS effect associated with the base minority carrier transport is modeled with a RC network, while the input NQS effect associated with the base-collector space charge region (CB SCR) carrier transport is modeled with a RLC network. With the proposed input NQS equivalent circuit model, Y-parameters and RF noise parameters using the van Vliet model are successfully modeled for frequencies up to fT. The transport noise model is extended to represent the van Vliet model by using two noise related time constants, which eliminates the need of Y-parameter in the description of the noise source. The input NQS effect for such model is verified to be important only for frequencies above fT/3. Analytical Y-parameter and noise solutions of a 1-D bipolar transistor at low injection level are used for validation.

A new method to directly extract base and emitter resistance parameters for SiGe HBTs using the Mextram bipolar compact transistor model has been presented. The method only requires a standard forward Gummel measurement and accounts for several second order effects like high-injection base conductivity modulation, Early effect and emitter current crowding. Base and emitter resistance parameters have been extracted over a wide temperature range (300K - 93K) for a first generation 0.5µm SiGe HBT with a peak cut-off frequency of 50 GHz at 300K. The HBT features a heavily doped poly-silicon emitter, an extrinsic base region doped well above the Mott's transition (3e18 cc for boron in silicon) and an intrinsic base region doped very close to the Mott's transition. The extracted parameters have been verified by comparison with several different methods.

The work presents a new physics-based compact model of trap-assisted tunneling (TAT) current in forward biased base-emitter junction. Such TAT current is negligible at room temperature, but becomes significant at cryogenic temperatures. Inclusion of TAT current and its separation from the total base current is not only important for lower VBE base current, but also affects extraction of the ideal base current. The model is successfully applied to a first-generation SiGe HBT technology from 43 to 110 K.

This work examines the individual impact of drift and diffusion charge collection in the collector-base (CB) and collector-substrate (CS) junctions on single-event-upset (SEU) in SiGe HBT current mode logic (CML) circuits. The CS junction diffusion charge collection has negligible impact on circuit SEU, despite its large charge collection magnitude. The CB and CS drift charge collection are primarily responsible for the observed SEU in CML circuits. The CB drift charge collection is as important as the CS drift charge collection, even though its charge magnitude is much less, because the resulting current excitation appears between collector and base nodes, and hence is amplified. Using selective ion track placement, we show that an ion track passing through the physical CS junction is much more effective in causing SEU than an ion track not passing through the CS junction because of potential funneling and consequent large induced drift current magnitude, which is necessary for SEU of CML circuit.

In this paper, we investigate the physics and modeling of temperature dependence of various parasitic resistances in SiGe heterojunction bipolar transistors down to 30 K. Carrier freezeout is shown to be the dominant contributor to increased resistances at cryogenic temperatures for lightly-doped and moderately-doped regions, whereas the temperature dependence of the mobility is the dominant contributor to the temperature dependence of heavily-doped regions. Two incomplete ionization models, the classic model with a doping dependent activation energy and the recent model of Altermatt , are shown to underestimate and overestimate incomplete ionization rate below 100 K for intrinsic base doping, respectively. Analysis of experimental data shows that the bound state fraction factor is temperature dependent and including this temperature dependence enables compact modeling of resistances from 30 to 300 K for moderately-doped regions. For heavily-doped regions, a dual power law mobility approximation with complete ionization is shown to work well down to 30 K. An alternative approach is also presented for heavily-doped resistors which allows one to use the same model equation for all regions.

This paper presents measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology. The IP3 sweet spot is actually at a V GS lower than zero K 3g m point. This V GS difference is attributed to the nonlinear output conductance and the cross terms using a Volterra-series-based IP3 expression. The impact of these nonlinearities is quantified using simulated I-V and device small-signal parameters extracted from S -parameter simulation. The scaling factors of the nonlinearities causes a decrease of IP3 sweet spot J DS as device size increases. The IP3 expression can accurately predicts the device size dependence of IP3 sweet spot. The frequency dependence of IP3 is determined by the small signal capacitance. Thus, the frequency dependence is very weak and negligible for a small device. For a large device, not only gate-source capacitance and drain-bulk capacitance, but also gate-drain capacitance are important. To determine the value of IP3 accurately, a more complete equivalent circuit of the MOS transistor must be used in Volterra-series analysis. The V DS dependence of the IP3 sweet spot V GS is primarily due to drain induced barrier lowering.

The general van Vliet noise model for transistors was derived for base minority carriers only under adiabatic boundary conditions. This paper extends the model by including the emitter minority carrier noise and the base–collector space charge region (CB SCR) effects based on the mathematical framework developed by van Vliet. Both the finite surface recombination velocity at polysilicon emitter and the finite carrier exit velocity at CB SCR are considered. It is proved that the van Vliet model can be directly used to include the emitter minority carrier noise, and the model holds when the two finite velocity boundary conditions are imposed. A new set of equations are derived to include the effect of CB SCR delay on noise.

This work presents 3-D mixed-mode simulation results of single event transients (SET) in SiGe HBT emitter followers. The impact of circuit design parameters, including biasing current and resistance are detailed. A simple increase of biasing emitter current is shown to be ineffective for hardening. Instead, during SET, the emitter voltage upset simply follows the base voltage upset due to the inherent nature of the emitter follower topology during circuit operation. The duration and the peak value of the base voltage upset are determined by the impedance and electric field between collector and base. As a result, the use of a smaller base biasing resistance is desirable for reducing SETs in emitter followers.

We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63 MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300 K to 77 K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50 Mbit/s to 4 Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300 K and 77 K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2 D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300 K and 77 K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures.

Microbeam measurements and TCAD simulations are used to examine the effects of ion angle of incidence on the charge collected from events occurring in a Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT). The results identify the geometrically driven charge-collection mechanisms that dominate the low LET broad beam SEU response. The deep trench isolation that surrounds the transistor significantly modulates the charge transport and, therefore, the charge collected by the collector. A new way of estimating critical charge, , for upset in SiGe HBT circuits is proposed based on TCAD simulation results and measured broadbeam data.

We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the DC nor AC performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made.

This work draws on experimental and simulation results to derive a generalized SEU response model for bulk SiGe HBTs. The model was validated using published heavy ion and new proton data gathered from high-speed HBT digital logic integrated circuits fabricated in the IBM 5AM SiGe BiCMOS process. Calibrating to heavy ion data was sufficient to reproduce the proton data without further adjustment. The validated model is used to calculate upset event rates for low-earth and geosynchronous orbits under typical conditions.

In this work we present a new circuit-level hardening technique for SEU mitigation in high-speed SiGe BiCMOS digital logic. A reduction in SEU vulnerability is realized through the implementation of an additional storage cell redundancy block to achieve the required decoupling. When compared with latch duplication, current sharing or gated feedback techniques, this method incurs a lower power penalty and no speed penalty. The hardened circuit is implemented in CML and LVL families and circuit simulation models predict significant reduction in the number of upsets compared to the corresponding unhardened versions. The technique is also easy to incorporate into existing designs.

This paper presents a SEU hardening approach that uses a dummy collector to reduce charge collection in the main transistor. The dummy collector is obtained using the silicon space between adjacent HBTs. It is obtained without any process modification or area penalty. The simulations are performed for normal and angled strikes. The hardened device shows significant reduction in charge collection due to sharing of diffusive charge collection by the dummy collector. Multiple HBT arrays of regular and hardened HBT are simulated to study the simultaneous charge collection in multiple HBTs. With hardening, charge collection in multiple devices is suppressed considerably for normal and angled strikes as the shared dummy collector collects a large amount of charge.

This paper presents a general 4-port algorithm that can remove on-wafer parasitics from on-wafer measurements after impedance standard substrate (ISS) calibration of system errors, or remove both system errors and on-wafer parasitics in a single step without ISS calibration. On-wafer standards are fabricated on a 0.13 RF CMOS process, and experimental data are measured from 2 to 110 GHz using an HP 8510XF system. The impact of nonideal on-wafer load standards is examined using the deembedded transistor-parameters and the extracted small signal parameters. The errors remaining after the traditional open-short deembedding are numerically evaluated, which become significant above 50 GHz. The solved 4-port network for on-wafer parasitics is indeed reciprocal despite the assumptions of ideal OPEN and SHORT, thus allowing a mathematically simpler reciprocal 4-port solution. The general 4-port solution can also be directly applied to the measured raw S-parameters to remove both system errors and on-wafer parasitics in a single step. Single-step calibration leads to reasonably accurate transistor -parameters, despite the less accurate on-wafer standards compared to precision ISS standards.

The inverse-mode operational regime of silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) has to date been largely ignored and is typically dismissed as a viable possibility for circuit applications due to the general perception of its limited dc and ac performance capabilities. In this paper, the inverse-mode performance of four distinct generations of SiGe HBTs is investigated and is found to improve impressively with generational scaling. The physics behind these scaling-induced improvements is examined in detail using a combination of measurements and calibrated simulations. A novel lateral dependence of the inverse-mode base current is identified and is shown to potentially present new opportunities for even larger improvements in inverse-mode performance in SiGe HBTs. A record peak fT in inverse mode of 25 GHz is reported for a prototype fourth-generation device

Residual levels of stress remaining after device fabrication have been characterized in the base and emitter regions of shallow-trench-isolated complementary npn and pnp transistors on (100) silicon utilizing uniaxial stress measurements. A residual biaxial stress of approximately 160 MPa has been found in the active regions of the npn transistors, whereas negligible residual stress is observed in the corresponding pnp transistors.

This work presents a dual-band transformer-based voltage controlled oscillator (VCO) with phase noise optimization. Transformers consisting of four inductors are employed to reduce area. Four cross-coupled VCO cores are connected to the four wings of two pairs of transformers to allow individual control of the cores, whose mutual inductance is utilized to enhance the frequency tuning. Also, the capability of transformer coupling for phase noise reduction is demonstrated. The proposed transformer-based VCO can oscillate at two frequency bands centered at 1.9GHz and 3.6GHz with around 30% tuning range for each band. Experimental implementation in a 0.18 urn SiGe BiCMOS technology demonstrates a measured phase noise of −114/119dBc/Hz and −115/120dBc/Hz at 1MHz offset for high and low bands, respectively.

We present, for the first time, an analysis of the error signatures captured during pulsed laser microprobe testing of high-speed digital SiGe logic circuits. 127-bit shift registers, configured using various circuit level latch hardening schemes and incorporated into the circuit for radiation effects self test serve as the primary test vehicle. Our results indicate significant variations in the observed upset rate as a function of strike location and latch architecture. Error information gathered on the sensitive transistor nodes within the latches and characteristic upset durations agree well with recently reported heavy-ion microprobe data. These results support the growing credibility in using pulsed laser testing as a lower-cost alternative to heavy-ion microprobe analysis of sensitive device and circuit nodes, as well as demonstrate the efficiency of the autonomous detection and error approach for high speed bit-error rate testing. Implications for SEU hardening in SiGe are addressed and circuit-level and device-level Radiation Hardening By Design recommendations are made