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30 results on '"Guo, Zhichuan"'

7. QGWFQS: A Queue-Group-Based Weight Fair Queueing Scheduler on FPGA.

Author

Guo, Yunfei, Guo, Zhichuan, Song, Xiaoyong, and Song, Mangu

Subjects
BANDWIDTH allocation, SWITCHING systems (Telecommunication), SOCIAL networks
Abstract

Weight Fair Queuing is an ideal scheduling algorithm to guarantee the bandwidth of different queues according to their configured Weights when the switching nodes of the network are congested. Many of the switching nodes based on FPGA in the current network support four physical ports or hundreds of virtual ports. Massive logic and storage resources would be consumed if each port implemented a WFQ scheduler. This paper proposes a Queue-Group-Based WFQ Scheduler (QGWFQS), which can support WFQ scheduling across multiple ports through the reuse of tag calculation and encoding circuits. We also propose a novel finish tag calculation algorithm to accommodate the variation in the link rate of each port. The remainder of integer division is also taken into account, which makes the bandwidth allocation fairer. Experimental results show that the proposed scheduler supports up to 512 ports, with 32 queues allocated on each individual port. The scheduler has the capability to operate at 200 MHz and the total scheduling capacity reaches 200 Mpps. [ABSTRACT FROM AUTHOR]

Published
2023
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9. Fast Update Algorithm With Reorder Mechanism for SRAM-Based Longest Prefix Matching on FPGA

Author

Song, Xiaoyong and Guo, Zhichuan

Abstract

Longest prefix matching (LPM) is often used in network forwarding and it is usually implemented by ternary content addressable memory (TCAM) on field programmable gate array (FPGA). The traditional SRAM based TCAM only has one clock cycle in search delay, but it has a non-negligible update latency. Different from the general TCAM words, the ternary bits in LPM words are arranged continuously from low bits to high, and the prefix lengths of words have some distribution characteristics on actual network traffics. In this brief, a design is proposed to reduce the update latency of LPM by fast update algorithm with reorder mechanism. The key idea is reorder LPM prefix and partition don’t care bits into each sub-prefix evenly in SRAM based LPM, so that the update latency in each sub-table would be minimized and the whole update latency would be reduced. The design of this brief is implemented on Xilinx Kintex-7 field-programmable gate array. Compared to the prior methods, the update latency of LPM is reduced by at least half or more in most cases with our method. As far as we know, this is the fastest update mechanism in SRAM based LPM, which consumes the least possible clock cycles.

Published
2024
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17. AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC

Author

Xiaoying Huang, Song Mangu, Guo Zhichuan, and Yunfei Guo

Subjects
reconfigurable accelerator, TK7800-8360, Computer Networks and Communications, Network packet, business.industry, Computer science, Packet processing, Throughput, Reconfigurable computing, Software, Hardware and Architecture, Control and Systems Engineering, SmartNIC, Embedded system, hardware acceleration, Signal Processing, Forwarding plane, Hardware acceleration, data plane, Electrical and Electronic Engineering, Electronics, Field-programmable gate array, business, FPGA
Abstract

Software-defined networking (SDN) has attracted much attention since it was proposed. The architecture of the SDN data plane is also evolving. To support the flexibility of the data plane, the software implementation approach is adopted. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. However, completely implementing the data plane on hardware weakens the flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput. We offloaded a cached-rule table to the proposed accelerator and tested its performance with 100 GbE traffic. Compared with the software implementation, the evaluation result shows that the throughput can achieve a 600% improvement when processing small packets and a 100% increase in large packet processing, and the latency can be reduced by about 20× and 100×, respectively, when processing small packets and large packets.

Published
2021
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26. A low complexity reversible data hiding method based on modulus function

Author

Wang Jin-lin, Ni Hong, and Guo ZhiChuan

Subjects
Modulo operation, Computer science, Information hiding, Speech coding, Watermark, Algorithm, Host (network), Digital watermarking, Transform coding
Abstract

In this paper, we proposed a low computational complexity lossless data hiding method. The data hiding method is based on modulus function. The basic idea of the algorithm is to compress the host data to create room for watermark. After watermark extraction, the host data can be exactly recovered. The algorithm also can be applied to near lossless data hiding with little modification. The low complexity lossless data hiding algorithm has successfully applied to speech signals and the hiding capacity is large. Finally, the experimental results have been given and the conclusions have been drawn.

Published
2008

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