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In this article, a novel high-speed floating-point multiply-accumulator (FPMAC) is proposed. It comprises a signed soft multiplier and a single-cycle floating-point accumulator (FAAC). The multiplier is realized by a radix-4 Booth encoding based on sign-magnitude inputs. The FAAC contains a bidirectional shift alignment, a fast 3:1 compressor, and a three-operand leading-zero predictor (LZP). Due to the simplification of implementation steps, a short critical path, and a full-pipelined structure, our FPMAC achieves a high running speed while sustaining the good performance of delay and resource consumption. We have implemented and evaluated our FPMAC on two devices from Xilinx. Compared with two contrast FPMAC architectures, the results show that the maximum clock frequencies of our FPMAC increase by 33.4%–74.4% in single-precision floating-point (SFP) and 15.8%–86.1% in double-precision floating-point (DFP).

For medium-voltage high-power drives, switching frequency is usually expected to be restricted to several hundred hertz to restrain the switching losses. In order to maintain small current distortions and torque ripples, synchronous symmetrical optimal PWM is an attractive option. Based on the closed-loop control method for induction motor using SHEPWM, a method that combines the optimal steady-state performance of SHEPWM with the fast dynamics of trajectory tracking control is proposed in this paper. The system uses feed-forward control to obtain the voltage reference, and applies stator flux trajectory tracking control when the stator flux error exceeds the limit to reduce the current impact in the transition. The proposed closed-loop control system satisfies both the steady-state as well as the dynamic performance requirements with a simplified structure. Reasonable current total harmonic distortion is maintained in steady-state operation while small current impact and fast dynamic response are achieved at low switching frequency. The effectiveness of the proposed method is validated by the simulation results obtained from NPC inverter-based induction motor drive system.

In the phase-shifted full-bridge circuit, the voltage spike caused by the hard turn-off of the switch tube increases the voltage stress of the switching device. Due to the existence of energy-consuming components such as resistance in the traditional absorption circuit, the efficiency is not always high. Based on the RCD snubber circuit, a low-loss absorption circuit is designed in this paper. This circuit absorbs voltage spikes through an absorption capacitor, and then slowly releases energy through an oscillating circuit consisting of current-limiting inductance, stray inductance, and absorption capacitance. The current-limiting inductance reduces the current stress of the blocking diode effectively, which can be achieved with the absorption not being affected and the power loss being reduced. Finally, the absorption effect and energy loss of the new low-loss absorption circuit and the commonly used RCD circuit were simulated and compared in PSpice software, and verified its feasibility.