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Micro-interconnection reliability analysis has been affected by a drastic solder joint size reduction and adoption of lead-free material. Furthermore, the current density in the solder joint has sharply increased. During actual operation, and under the action of thermal-electrical coupled stress, voids caused by atom migration appear in the solder joint and affect its reliability. In this study, a phase-field model considering the coupled stress is proposed to simulate the void evolution in solder joints and analyse the effect of coupled stress. Single- and double-void growths are simulated, as well as void migration. The results showed that the coupled influence of thermal and electrical stresses collectively contributed to the void growth. The effects of current density and temperature are positive. A higher external stress resulted in a higher growth rate. Double voids can grow independently or coalesce together, depending on the initial spacing of the centres of the two voids. The shorter the spacing, the less the time consumed on the procedure. However, it has a slight effect on the void growth dynamics. The void migration simulation revealed that a higher temperature gradient accelerates the migration velocity. In addition, there is an inverse relationship between the migration velocity and radius. This study provides a specific phase-field model to simulate void growth in lead-free solder joints under thermal-electrical coupled stress.

Photo response nonuniformity (PRNU) is a crucial parameter in evaluating and choosing CMOS image sensors. The current methods and standards use the integrating sphere to illuminate the sensor and assume a known uniform illumination. And PRNU is calculated based on the spatial variance of images. In practice, the uniformity of illuminance can be hardly guaranteed. A slight nonuniformity will cause a significant increase in spatial variance and bring unacceptable evaluation errors. In this article, we present a novel method to estimate PRNU of linear CMOS image sensors. The method allows nonuniform illumination and does not require specific settings for the light source and sensors. First, an observation model is established for the data of nonuniformly exposed images. The model is composed of an irradiance model and a noise model. The irradiance model describes the original output, and the noise model depicts the noise variance as a function of local illuminance. PRNU is a parameter in the noise model to be estimated. Then, the model parameters including PRNU are estimated by a two-stage method based on maximum likelihood estimation. We also use simulations to validate the developed methods and demonstrate the robustness of the model under sensor misalignment. Finally, the proposed method is illustrated by a measurement experiment.

As a critical device of power electronics, the health status and residual life of the insulated gate bipolar transistor (IGBT), as well as its high-efficiency assessment should be concerned. High-efficiency assessment methods can provide dangerous warning for transportation equipment to avoid catastrophic accidents. This article focuses on the IGBT solder layer failure. We use the finite element simulation combined with the small current junction temperature measurement method to obtain the relationship between the internal structure degradation of the solder layer and the sensitive parameters of the external port under different load conditions. According to the characteristics of port parameters, a data processing method called multiple weight function (WF) network (MWFN) is developed, and the parameter monitoring platform is built. Finally, an IGBT health assessment method based on MWFN is formed. The main advantage of this method is that the best WF is introduced into the neural network to solve the time-consuming problem of updating the high-dimensional weight matrix. In the case study, the active power cycling test was carried out. We obtained the solder layer delamination images by using the 3-D tomography system and the corresponding port parameters by monitoring platform. From the perspective of evaluation results, the proposed method not only performs as well as other mainstream data-driven methods in terms of evaluation accuracy but also has significant advantages in terms of running time.

The physics-of-failure (PoF) technique is a practical approach to evaluate the reliability of semiconductor devices. However, the PoF approaches are usually insufficient in dealing with multi-mechanism failure and fitting the Monte Carlo (MC) sampling data. In our study, we propose an improved reliability evaluation method based on PoF technique and maximum entropy (MaxEnt) principle. The PoF models are used to generate time-to-failure samples of the failure mechanisms. Cumulative damage rules and competing failure rules are adopted to deal with multi-point and multi-mechanism failure and generate lifetime samples of the device. And the lifetime samples are fitted by MaxEnt distributions through the proposed fitting algorithm. The numerical examples given in the paper indicate that the MaxEnt distributions can describe the samples well and have a competitive advantage in dealing with multi-peak samples. A case study about a semiconductor device with multi-mechanism failure is presented to explain the workflow of the proposed reliability evaluation approach. The results show that the proposed MaxEnt distributions can yield reliable reliability evaluation results compared with Weibull and Lognormal distributions in the multi-mechanism failure process.

Atmospheric corrosion is one of the most common failure phenomena in copper-containing components of areoengine due to corrosive gases and high temperature. This paper described a failure analysis of hall-effect sensors in an areoengine brushless direct-current (BLDC) starter/generator. The failure analysis experiments were performed with electrical performance test, external visual inspection, X-ray inspection, internal visual inspection, scanning electron microscope (SEM) and energy dispersive spectroscopy (EDS). Short-current failure was ascertained as failure mode of the hall-effect sensors by electrical performance test. Internal visual inspection, SEM and EDS were conducted to determine the failure mechanism of the samples as copper sulfide (Cu2S) corrosion. Moreover, validation experiments were carried out to confirm the results of failure analysis in which the failure of another sample was stimulated under 120 Centigrade for three hours. Some failure causes of the hall-effect sensors were inferred and some recommendations for the optimum design of hall-effect sensor modules were elaborated.

Rolling bearing is a very essential component of the industrial machinery. The bearing fault could cause a significant loss. Therefore, it is necessary to perform fault diagnosis and prediction on the bearing. This paper combines Ensemble Empirical Mode Decomposition (EEMD), Singular Value Decomposition (SVD) difference spectrum de-noising, and the convolutional neural network (CNN) to realize the diagnosis and prediction of bearing faults. EEMD is used to extract features, and SVD difference spectrum de-noising is used to denoise the decomposed signals. The reconstructed vibration signals are then fed into CNN to realize fault diagnosis. Further, by analyzing the output of the softmax layer after the input of testing sets, the prediction of bearing fault can be realized. The bearing vibration signals are used to perform diagnosis. And we use partial samples of bearing fault full-period data to retrain CNN for prediction. In this paper, these methods successfully lead to bearing fault diagnosis with high accuracy and early bearing fault prediction.

With the development of deep-space exploration, electronic components and integrated circuits in the spacecraft must face the harsh environment in deep space, including cryogenic temperature. For CMOS devices, cryogenic temperature may cause issues in reliability. To qualify the normal application of CMOS devices, an evaluation method of CMOS devices at cryogenic temperature based on stress-strength interference theory was proposed. Moreover, according to the method, stress-strength interference models were built to calculate the failure probability of SN74AHC14 CMOS Inverters at cryogenic temperature.

The accurate prognosis of fatigue crack growth (FCG) is vital for securing structural safety and developing maintenance plans. With the development of structural health monitoring (SHM) technology, the particle filter (PF) has been considered a promising tool for online prognostics of FCG. Among the existing FCG models, the traditional Paris-Erdogan model is most commonly used in PF-based FCG prognostics. The parameters of the Paris-Erdogan model can be estimated together with the crack state in the PF framework. However, we find that there is a problem of “Coordinated Change” when the parameters priors are far from the true values. As a result, the filtering results appear as a correct remaining useful life (RUL) prognosis but an incorrect parameters estimation. To solve this problem, in this paper, a novel recursive least squares-kernel smoothing (RLS-KS) method is proposed for parameter estimation in PF-based FCG prognostics. The proposed method is validated through an experimental application; and then compared with the classic artificial evolution (AE) and kernel smoothing (KS) methods. The validation results show that the RLS-KS method can provide both correct RUL prognostics and parameter estimation. Moreover, this method provides better performance for FCG prognostics compared with classic methods.

To verify the reliability of a typical Pb-free circuit board applied for space exploration, five circuits were put into low temperature and shock test. However, after the test, memories on all five circuits were out of function. To investigate the cause of the failure, a series of methods for failure analysis was carried out, including X-ray detection, cross-section analysis, Scanning Electron Microscope (SEM) analysis, and contrast test. Through failure analysis, the failure was located in the Pb-free (Sn-3.0Ag-0.5Cu) solder joint, and we confirmed that the failure occurred because of the low temperature and change of fracture characteristic of Sn-3.0Ag-0.5Cu (SAC305). A verification test was conducted to verify the failure mechanism. Through analyzing data and fracture surface morphology, the cause of failure was ascertained. At low temperature, the fracture characteristic of SAC305 changed from ductileness to brittleness. The crack occurred at solder joints because of stress loaded by shock test. When the crack reached a specific length, the failure occurred. The temperature of the material&rsquo, s characteristic change was &minus, 70 &deg, C&ndash, &minus, 80 &deg, C. It could be a reference for Pb-free circuit board use in a space environment.

Liquid crystal display (LCD) is likely to accumulate charge and incur ESD events due to the insulating glass plate. In our study, an ESD induced failure of interconnects in LCD gate driver on array (GOA) was analyzed. The monochrome pattern test was conducted to locate the failure site. The morphology of the failure site was characterized by SEM, EDS and FIB. Charge accumulation on long interconnects in the VUV-cleaning process, and subsequent discharging damage at narrow interconnect gaps were analyzed to be the root cause of failure. Furthermore, some specimens were designed to validate the analysis, design of experiments was performed to study the effects of the gap space and the interconnect length on the failure severity. Based on the experimental data, a logistic model was developed to model the failure severity, which can help to provide suggestions for designs to reduce the incidence of failures.

Purpose The purpose of this paper is to present a failure analysis of the solder layer in a Darlington power transistor in a TO-3 package. Design/methodology/approach A failed Darlington power transistor in a TO-3 package was examined by different kinds of failure analysis techniques. At first, internal gas analysis was conducted to measure the atmosphere. Then, scanning acoustic microscopy (SAM) was performed to check the quality of the solder layers in the failed device, and the failure location was determined in the solder layer between chip and substrate. Next, the failed device was decapped to observe the defects. After removing the chip from the substrate, energy dispersive spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) were applied and the main elemental composition of the solder layer was identified. Findings Internal gas analysis indicated that the moisture and oxygen contents exceeded the allowed maximum value. Large areas of voids were found in the solder layer by SAM. The main elemental compositions of the solder layer were identified by scanning electron microscopy and EDS. Furthermore, the valences of the chemical components in the solder layer were identified by XPS. Except for the few simple substances of the initial solder material, the chemical formulae of oxidation products in the solder layer were deduced. In addition, the root causes are also discussed. Originality/value This paper focuses on the solder layer failure of a power transistor. Factors such as the presence of oxygen, voids and other factors, which can cause transistor damage, were comprehensively analyzed. The analysis process is worth learning from and the results can be used to improve the reliability of power devices in this kind of package.

Sintering Ag materials is a promising candidate for the die-attachments in SiC power devices due to its high melting point and low thermal resistance. However, CTE mismatch between the SiC chips and the substrates causes cracks to develop in the sintered interconnection structures. Power cycling conditions lead to periodic loadings on the Ag sintering die-attachment. The incremental accumulation of plastic strain energy, combined with periodic fluctuations of elastic strain energy, results in the fatigue crack evolutions of the sintered structures. Further, the crack evolutions considerably degrade the thermal and mechanical properties of the interconnect structure, and critically affects the integrity of the heat transfer network and the mechanical structure of the power devices. In this paper, the fatigue crack evolution of Ag sintering die-attachment in the SiC power devices is simulated based on the phase-field models. Moreover, the thermal performance degradations and stress distributions of die-attachment under power cycling are analysed. A methodology based on finite element modelling and phase-field simulation is proposed, realised by Abaqus and its subroutines. The fatigue crack in the Ag sintering die-attachment initiates from the chip-side corner point, then propagates to the chip-side centre point until the formation of a penetrative crack, which achieves a good match with experimental results. Moreover, along with the crack propagation, the thermal distributions in the chip and the stress distributions of the sintering layer are obtained to analyse the degradations of thermal and mechanical performances of Ag sintering die-attachment in SiC power devices.

The thermal stability of silver (Ag) paste sintering on coated copper (Cu) and aluminum (Al) substrates has been investigated. Instead of conventional zincating or nickel plating, magnetron sputtering was used to achieve coating with titanium (Ti) and Ag. Silicon (Si) chips were bonded to coated Cu and Al substrates using a mixture of submicron Ag flakes and particles under 250°C and 0.4 MPa for 30 min. The joints were then subject to aging testing at 250°C for duration of 200 h, 500 h, and 1000 h. Two types of joints exhibited satisfactory initial shear strength above 45 MPa. However, the shear strength of the joints on Al substrate decreased to 28 MPa after 1000 h of aging, while no shear strength decline was detected for the joints on Cu substrate. Fracture surface analysis revealed that the vulnerable points of the two types of joints were (1) the Ag layer and (2) the interface between the Ti layer and Cu substrate. Based on the results of scanning electron microscopy (SEM), energy-dispersive x-ray spectroscopy (EDS), and simulations, cracks in the Ag layer were identified as the cause of the shear strength degradation in the joints on Al substrate. The interface evolution of the joints on Cu substrate was ascribed to Cu migration and discontinuity points that initialized in the Ti layer. This study reveals that Al exhibited superior thermal stability with sintered Ag paste.

Due to their growing power and shrinking size, thermal management and analysis have become one of the most critical concerns for power devices. Though finite element (FE) method is commonly employed in thermal analysis now, the uncertainty of material properties and the redundancy of repeat modeling still nag analyzers. In this paper, a simplified approach for steady thermal analysis of chips with variable power is proposed. Based on spatial autocorrelation and undetermined method, the steady temperature distribution could be directly determined with power distribution and example temperature measurement result, without identifying environment factors or material properties. The theory of the simplified approach is introduced at first in this paper. The characteristics of the simplified approach are discussed afterwards. Eventually, a case study is given to illustrate the procedure, of which the analytical result coincides with the actual measurement well.

In this study, a physics-based compact model for high-speed buffer layer insulated gate bipolar transistor (IGBT) is proposed. The model utilizes the 1-D Fourier-based solution of ambipolar diffusion equation (ADE) implemented in MATLAB and Simulink. Based on the improved understanding on the inductive switching behavior of a high-speed buffer layer IGBT, the ADE is solved for all injection levels instead of high-level injection only as usually done. Assuming high-level injection condition in the buffer layer, the excess carrier transport, redistribution and recombination in the buffer layer are redescribed. Moreover, some physical characteristics such as the low conductivity of N-base at turn-on transient and free holes appeared in the depletion layer during turn-off process are also considered in the model. Finally, the double-pulse switching tests for a commercial field stop IGBT and a light punch-through carrier-stored trench bipolar transistor are used to validate the proposed model. The simulation results are compared with experiment results and good agreement is obtained.

The voltage and current oscillations occasionally occur during the reverse recovery transient of the superjunction MOSFET body diode. This paper identifies the unique reverse recovery oscillation characteristics of the superjunction MOSFET body diode. Base on the experimental investigation and theoretical analysis, the various reverse recovery oscillation mechanisms are clarified. At first, with a discrete 650 V/47 A superjunction MOSFET utilized, the high-frequency and low-frequency oscillation characteristics during the reverse recovery transient are obtained by the double-pulse test. After the theoretical analysis, it is found that the superjunction MOSFET body diode has various oscillation mechanisms depending on its drift region injection level. Under high-level injection condition, the high-frequency oscillation occurs due to the plasma extraction transient-time (PETT) effect. Under low-level injection condition, the body diode’s snappy reverse recovery results in the low-frequency LC oscillation. In the end of the paper, the oscillation behaviors under both high and low level injection conditions are reproduced by the mixed-mode numerical simulation, the simulation results validate the proposed oscillation mechanisms.

The dynamic avalanche has a huge impact on the switching robustness of carrier stored trench bipolar transistor (CSTBT). The purpose of this work is to investigate the CSTBT’s dynamic avalanche mechanism during clamped inductive turn-off transient. At first, with a Mitsubishi 600 V/150 A CSTBT and a Infineon 600 V/200 A field stop insulated gate bipolar transistor (FS-IGBT) utilized, the clamped inductive turn-off characteristics are obtained by double pulse test. The unclamped inductive switching (UIS) test is also utilized to identify the CSTBT’s clamping voltage under dynamic avalanche condition. After the test data analysis, it is found that the CSTBT’s dynamic avalanche is abnormal and can be triggered under much looser condition than the conventional buffer layer IGBT. The comparison between the FS-IGBT and CSTBT’s experimental results implies that the CSTBT’s abnormal dynamic avalanche phenomenon may be induced by the carrier storage (CS) layer. Based on the semiconductor physics, the electric field distribution and dynamic avalanche generation in the depletion region are analyzed. The analysis confirms that the CS layer is the root cause of the CSTBT’s abnormal dynamic avalanche mechanism. Moreover, the CSTBT’s negative gate capacitance effect is also investigated to clarify the underlying mechanism of the gate voltage bump observed in the test. In the end, the mixed-mode numerical simulation is utilized to reproduce the CSTBT’s dynamic avalanche behavior. The simulation results validate the proposed dynamic avalanche mechanisms.

CMOS image sensors are extensively utilized in digital imaging systems for their excellent performance and low power consumption. As an essential components in the system, CMOS image sensors are expected with low noise levels. The images captured by CMOS image sensor contain random noise (RN), digital noise (DN), and fixed pattern noise (FPN). FPN of CMOS image sensors has a greater impact on the perceived image quality than random noise, which seriously restricts the development and application of CMOS image sensors. This paper proposed a noise power spectrum (NPS) method for estimating column FPN of CMOS image sensor based on AR model. First, dozens of images under uniform illumination are acquired by established test vehicle. Second, random noise of the images is restrained by using the multi-frame averaging method. Then, column FPN is modeled by an autoregressive (AR) random process subsequently. Ultimately, column FPN is estimated by calculating NPS of the image based on the AR model. A case application was proposed by using this method.

This paper proposes a method to identify damage-sensitive electrical parameters (DESPs) for insulated gate bipolar transistor (IGBT) bond wires. Multiphysics simulations are performed to emulate the realistic electrical, thermal and mechanical behaviors of IGBT module. Temperature-dependent material properties are considered in silicon chips and aluminum bond wires. Steady-state electro-thermo-mechanical simulation results of IGBT modules in a given collector current are presented. The degradation mechanisms of wire-bonding crack propagation and complete lift-off are explored. Simulations are validated through the power cycling tests. The trend of measured forward voltage V CE(on) is similar to the simulation result. The modeling method and results can be used to evaluate the health status of IGBT module bond wires.

Fatigue crack is an important factor affecting structural safety, and it is of great significance for accurate monitoring of fatigue crack propagation. This paper presents a Lamb Wave-based method for quantitative monitoring of fatigue crack propagation. In this method, various types of damage features are extracted in both time and frequency domains to comprehensively describe the Lamb wave changes. To address the problem of multicollinearity in damage features, principal component regression (PCR) is adopted to establish a quantitative model between damage features and crack size. The PCR model is established and validated by the experimental data of aluminum alloy plates. Experimental results reveal that the proposed PCR model is able to accurately monitor the fatigue crack propagation, and it performs far better than traditional multiple linear regression (MLR) model.

Nano-silver paste is an emerging lead-free bonding material in power electronics, and has excellent mechanical properties , thermal conductivity and long-term reliability. However, it is extremely challenging to model the mechanical and failure behaviours of sintered nano-silver paste due to its random micro-porous structures and the coupled thermomechanical loading conditions. In this study, a novel computational framework was proposed to generate the random micro-porous structures and simulate their effects on mechanical properties and fracture behaviour based on the one-cut gaussian random field model and the thermo-elasto-plastic phase-field model. The elastic modulus, ultimate tensile strength and strain to failure are computed statistically, showing good agreement with the experimental results. Further, the framework was applied to model the fracture of sintered nano-silver paste under thermal cyclic conditions, demonstrating the formation of distinctive crack patterns and complex crack networks. The cracking behaviours observed in the experiments and simulations are remarkably similar to each other. The framework was implemented within Abaqus via a combination of subroutines and Python scripts , automating the process of model generation and subsequent computation. This study provides an efficient and reliable approach to simulate the mechanical and failure behaviours of sintered nano-silver paste with random micro-porous structures.

In this study, a physics-based model for emitter controlled (EMCON) p–i–n diode is proposed. The model is based on the one-dimensional Fourier-based solution of ambipolar diffusion equation (ADE) implemented in MATLAB and Simulink. The ADE is solved for all injection levels based on the design concepts of EMCON diode. The deep field stop layer utilised in the EMCON diode is also considered in the solution. Moreover, the depletion behaviour in the N-base during reverse recovery is redescribed. To be self-contained, a parameter extraction method is proposed to extract all the parameters of the model. In the end, the static and reverse recovery experiments for a commercial EMCON diode are used to validate the proposed model. The simulation results are compared with experiment waveforms and good agreement is obtained.

Considering that moisture is a crucial factor affecting Plastic Encapsulate Microcircuits (PEMs), several test methods, including Temperature Humidity Bias (THB), autoclaving, and Highly Accelerated Stress Test (HAST), were proposed to assess the moisture resistance capacity of PEMs. To investigate the impact of moisture on PEMs, one certain type of Metal-Oxide -Semiconductor Field Effect Transistor (MOSFET) was selected as a representative of PEMs and underwent an autoclaving in this paper. The results demonstrate that the influences of moisture are diverse. Then a series of analyses, including electrical testing, Scanning Acoustic Microscope (SAM), bond pull testing, metallurgical microscopy, surface and cross-sectional analysis by Scanning Electron Microscope (SEM) and Energy Dispersive Spectrometer (EDS), were conducted to determine the failure cause. With the analyses, the increase of static drain-to-source on resistance is ascribed to surface oxidation. Besides, the moisture invading from the crack along the die side is deemed to contribute to the leakage current failure and the function failure. Finally, some suggestions are proposed to protect PEMs against moisture.

In this study, a physics-based model for the fast p-i-n diode is proposed. The model is based on the 1-D Fourier-based solution of ambipolar diffusion equation (ADE) implemented in MATLAB and Simulink. The physical characteristics of fast diode design concepts such as local lifetime control (LLC), emitter control (EMCON) and deep field stop are taken into account. Based on these fast diode design concepts, the ADE is solved for all injection levels instead of high-level injection only as usually done. The variation of high-level lifetime due to local lifetime control is also included in the solution. With the deep field stop layer taken into consideration, the depletion behavior in the N-base during reverse recovery is redescribed. Some physical effects such as avalanche generation and carrier recombination in the depletion region are also taken into account. To be self contained, a parameter extraction method is proposed to extract all the parameters of the model. In the end, the static and reverse recovery experiments for a commercial EMCON diode and a LLC diode are used to validate the proposed model. The simulation results are compared with experiment results and good agreement is obtained.

In this study, a physics-based model for light punch through (LPT) carrier stored trench bipolar transistor (CSTBT) is developed. The model is based on the Fourier series solution of ambipolar diffusion equation implemented in MATLAB and Simulink. In the model, the MOS-side two-dimensional (2D) effects resulting from trench gate and carrier storage layer are studied analytically. Assuming high-level injection in LPT buffer layer, the model also describes the carrier transport, redistribution and recombination in the buffer layer in details. The static and transient experiments for a commercial CSTBT are used to validate the presented model. The simulation results are compared with experiment results and good agreement is obtained.

An excess carrier lifetime extraction method is derived for physics-based insulated gate bipolar transistor (IGBT) models with consideration of the latest development in IGBT modeling. On the basis of the 2D mixed-mode Sentaurus simulation, the clamp turn-off test is simulated to obtain the tail current. The proposed excess carrier lifetime extraction method is then performed using the simulated data. The comparison between the extracted results and actual lifetime directly obtained from the numerical device model precisely demonstrates the accuracy of the proposed method.

The main purpose of the reliability enhancement test is to expose the weakness of the components in order to improve the process structure design. The current domestic test standards are Accelerated stress test procedures for electric and electronic products, Guidance on the definition and application of high-acceleration tests for avionics and so on. However, these standards have relatively broad provisions on test conditions. The feasible test schemes are not unique that lead to different required test conditions and test costs. The emerging device fiber optical acousto-optic modulator is expensive and the test cost is high. How to choose an efficient enhanced test program is particularly important. Based on the fuzzy theory, an optimization design method for the enhancement test of the fiber-optic acousto-optic modulator is established in this paper. This paper takes the test cost-efficiency ratio as the optimization target, and uses the reliability estimation deviation and cost as the fuzzy evaluation index for optimizing and designing of the enhancement test plan. Finally, the feasibility of the method is verified by case analysis.