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Digital optical data storage and processing are rapidly increasing in technological importance. The magneto-optic spatial light modulator (MOSLM) is a relatively low-cost, small pixel optical parallel input device that is capable of binary amplitude or binary phase modulation of each pixel. Thus, it is well matched to digital optical coherent storage and processing technology. However, potential problems associated with its use include: lack of a design for a general minicomputer interface, lack of interactive data-page file generation software, lack of ability to switch single pixels in some cases, lack of remote-from-computer operation capability, spurious pixel switching, and catastrophic failure due to thermal effects. The hardware and software components of a versatile minicomputer interface that has been successful in overcoming all of these problems are described. This interface allows easy data entry of entire data pages or single pixels and minimizes cross talk and noise developed over long cable lengths. In tests, the designed interface has produced highly stable operating characteristics. [ABSTRACT FROM AUTHOR]

The content-addressable network (CAN) is an efficient, intrinsically discrete training algorithm for binary-valued classification networks. The binary nature of the CAN network permits accelerated learning and significantly reduced hardware-implementation requirements. A multilayer optoelectronic CAN network employing matrix-vector multiplication was constructed. The network learned and correctly classified trained patterns, gaining a measure of fault tolerance by learning associative solutions to optical hardware imperfections. Operation of this system is possible owing to the reduced hardware accuracy requirements of the CAN learning algorithm.

A block-quantized binary-phase hologram consisting of a binary-phase hologram and a phase mask is investigated for use in optical interconnection. A simulated annealing algorithm is used to determine the phase pattern of the binary hologram and the phase of the mask required to achieve high diffraction efficiency and suppression of unwanted spots. Block-quantized binary-phase holograms encoded with the simulated annealing algorithm are fabricated using electron-beam lithography and chemical etching. The results from the optical experiments that use these holograms agree well with those from the computer simulations.

The simulated annealing algorithm is applied to the design of binary holographic optical elements for the connection of single-mode structures. The system energy used with the simulated annealing algorithm is the absolute square of the overlap between the transmitted wave front and the modal characteristics of the receiving device; the system variables are the binary states of the hologram pixels. The plausibility of the obtained binary patterns is discussed for examples involving plane and spherical modal characteristics. The ability of the annealing process to avoid local minimum trapping is demonstrated.

A binary phase only filter is encoded using a simulated annealing algorithm to distinguish two similar characters. Characters that cannot be distinguished with conventional filter encoding methods are clearly distinguished with the annealed binary phase only filter in a computer simulation. Two binary phase only filters have been fabricated by use of electron beam lithography and chemical etching. One is an annealed binary phase only filter, and the other is a binary phase only filter encoded with a conventional method. Optical pattern recognition experiments using the filters agree well with computer simulation results.

Analytic criterion for choice of the optimum phase in binary phase-only filters that will provide high correlation performance in optical image recognition is developed.

A binary phase only filter is encoded with a simulated annealing algorithm to classify two similar characters in a variety of fonts. Characters that cannot be distinguished with conventional filter encoding methods are clearly distinguished with the optimized binary phase only filter using a simulated annealing algorithm. This method gives zero error classification rate for tested characters. Correlation performance of the optimized binary phase only filter is compared with the binary phase only filters encoded with conventional methods. The computational requirements for optimizing the filter are not excessive.

A family of new interconnection networks, termed the nested crossbar, has been developed. These networks are particularly well suited to optical interconnects due to their high bisection width and high degree of space invariance. Algorithms have been developed for computing vector-matrix multiplication with nested crossbar connected processor arrays with time growth rates between O(1) and O(N(1/2)). (N is the number of elements in the vector.) When these algorithms are implemented on holographic optically interconnected very large scale integrated processor arrays, the nested crossbar networks have area and time growth rates close to fundamental lower bounds. The nested crossbar networks also allow the use of a minimum number of transmitters and detectors.

Optically interconnected processor arrays are compared to conventional fully electronic processor arrays in terms of interconnect density capabilities. A complexity model is introduced that allows the calculation of the array area growth rate as an asymptotic function of the number of processing elements in the array Lower bounds on the area growth rate of electrically interconnected processor arrays are compared to upper bounds for free-space optically interconnected circuits that employ computer generated holograms. Results indicate that for connection networks such as the hypercube, perfect shuffle and crossbar networks, that have a high minimum bisection width (a measure of the global nature of an interconnect topology) and contain some degree of spatial invariance, optically interconnected circuit area growth rates are below lower bounds on VLSI circuit growth rates.

The use of computer generated holographic elements for implementation of free-space optical interconnection of very large scale integrated circuits is presented. The design of the holographic optical elements is based on laser source divergence, source to hologram spacing, signal fanout, and resolution of the hologram recorder. The results of a computer simulation of diffraction from the hologram are compared with the analytically predicted results, particularly to confirm the effect of spatial sampling on the performance of an on-axis interferogram hologram. Measurements taken using transmission absorption and transmission phase holograms in photographic emulsion, as well as reflective surface relief holograms on silicon, are compared to predicted results. Performance benefits expected from extension of the design process to holograms fabricated using electron-beam lithography are discussed.

Computer Aided Design (CAD) systems that have been developed for electrical and mechanical design tasks are also effective tools for the process of designing Computer Generated Holograms (CGHs), particularly when these holograms are to be fabricated using electron beam lithography. CAD workstations provide efficient and convenient means of computing, storing, displaying, and preparing for fabrication many of the features that are common to CGH designs. Experience gained in the process of designing CGHs with various types of encoding methods is presented. Suggestions are made so that future workstations may further accommodate the CGH design process.

An iterative discrete on-axis encoding method for computer-generated holograms (termed IDO encoding) has been developed. The binary IDO method employs simulated annealing to optimize the hologram phase delay and reduce sensitivity to fabrication tolerances. Computer-simulation results indicate that binary phase IDO encoding is capable of generating two-dimensional spot arrays with diffraction efficiencies larger than 70%. An experimentally fabricated hologram, designed to account for a 6% manufacturing hologram thickness tolerance, produced a 3 x 3 array of spots with 59% diffraction efficiency. The binary IDO algorithm can be employed to encode arbitrary images with twofold rotation symmetry.

The suitability of various binary encoding methods for electron-beam recording of computer generated holograms is systematically evaluated. Subjected to the limitations of computing resources, a set of criteria is established according to which these encoding schemes are evaluated and compared. This comparison can be used to determine the optimum encoding method for desired wavefront properties.

The parallelism and interconnectivity of optical systems may provide important advantages for these systems in massively parallel processing applications. Electronic systems, however, retain all the advantages of a highly developed technology that has been widely applied with excellent success. In both of these technologies, the methods of direct truth-table look-up processing are becoming increasingly important as the need grows for increased speed and throughput. A major issue in truth-table look-up processing is the number representation used for data. In this paper, the effects of number representation are investigated for the important case of 8-bit addition as a specific example. The inputs are two 8-bit binary numbers together with an input carry. The output is a full precision 9-bit binary sum. For the intermediate processing three number representations are treated: binary, residue, and modified signed-digit. The numbers in all three representations are in binary-coded form throughout the processing. The critically important steps of encoding the numbers into the residue and modified signed-digit systems and then decoding the results back into direct binary are also performed using truth-table look-up methods. For the direct binary representation, a total of 2545 gates (2519 holograms) are required. For the residue representation, a total of 1764 gates (1686 holograms) are required. For the modified signed-digit representation, a total of 4142 gates (4052 holograms) are required.

A simulated annealing algorithm is introduced to encode binary phase-only filters optimally for image recognition. Similar patterns that cannot be distinguished with conventional filter encoding methods are clearly distinguished with the optimized filter. The computational requirements for optimizing the filter are not excessive.

The bidirectional associative memory (BAM) is a powerful neural network paradigm that is well suited to optical implementation. The BAM is heteroassociative (of which autoassociative operation is a special case) and is guaranteed to converge to a stable final state regardless of the connection weight matrix used. The BAM is placed in a conceptual framework that facilitates comparison with other neural network models. Variations on the BAM such as the bidirectional optimal memory (BOM), the competitive BAM (CBAM), and the adaptive BAM (ABAM) indicate some of the interesting directions this simple structure may evolve, leading in a natural progression toward the power of a model such as the Carpenter-Grossberg ART. The simplicity of the BAM invites uncomplicated optical implementations. BAM designs based on optical matrix-vector multipliers (MVMs) and on volume holographic connections are presented. Spatial light modulator (SLM) device designs currently under development to support the MVM BAMs are given.

Conditions are determined for which optical interconnects can transmit information at a higher data rate and consume lc3s power than the equivalent electrical interconnections. The analysis is performed for free-space optical intrachip communication links. Effects of scaling circuit dimensions, presence of signal fan-out, and the use of light modulators as optical signal transmitters are also discussed.

An upper bound on the area of a computer generated hologram (CGH) required to form space variant connections between N transmitters and N x F detectors is determined. The analysis is performed without employing paraxial or small transmitter divergence angle approximations. It is shown that a previously proposed method for performing space variant interconnects has limited usefulness for connecting transmitters with large divergence angles. A new architecture employing a double pass CGH is introduced, and an expression is derived for the interconnect density capabilities of this architecture.