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Global collaboration in cardio-oncology is needed to understand the prevalence of cancer therapy-related cardiovascular toxicity in different risk groups, practice settings, and geographic locations. There are limited data on the socioeconomic and racial/ethnic disparities that may impact access to care and outcomes. To address these gaps, we established the Global Cardio-Oncology Registry, a multinational, multicenter prospective registry.We assembled cardiologists and oncologists from academic and community settings to collaborate in the first Global Cardio-Oncology Registry. Subsequently, a survey for site resources, demographics, and intention to participate was conducted. We designed an online data platform to facilitate this global initiative.A total of 119 sites responded to an online questionnaire on their practices and main goals of the registry: 49 US sites from 23 states and 70 international sites from 5 continents indicated a willingness to participate in the Global Cardio-Oncology Registry. Sites were more commonly led by cardiologists (85/119; 72%) and were more often university/teaching (81/119; 68%) than community based (38/119; 32%). The average number of cardio-oncology patients treated per month was 80 per site. The top 3 Global Cardio-Oncology Registry priorities in cardio-oncology care were breast cancer, hematologic malignancies, and patients treated with immune checkpoint inhibitors. Executive and scientific committees and specific committees were established. A pilot phase for breast cancer using Research Electronic Data Capture Cloud platform recently started patient enrollment.We present the structure for a global collaboration. Information derived from the Global Cardio-Oncology Registry will help understand the risk factors impacting cancer therapy-related cardiovascular toxicity in different geographic locations and therefore contribute to reduce access gaps in cardio-oncology care. Risk calculators will be prospectively derived and validated.

We propose a generalized architecture for the first rapid-single-flux-quantum (RSFQ) associative memory circuit. The circuit employs hyperdimensional computing (HDC), a machine learning (ML) paradigm utilizing vectors with dimensionality in the thousands to represent information. HDC designs have small memory footprints, simple computations, and simple training algorithms compared to superconducting neural network accelerators (SNNAs), making them a better option for scalable SFQ machine learning (ML) solutions. The proposed superconducting HDC (SHDC) circuit uses entirely on-chip RSFQ memory which is tightly integrated with logic, operates at 33.3 GHz, is applicable to general ML tasks, and is manufacturable at practically useful scales given current SFQ fabrication limits. Tailored to a language recognition task, SHDC consists of 2-20 M Josephson junctions (JJs) and consumes up to three times less power than an analogous CMOS HDC circuit while achieving 78-84% higher throughput. SHDC is capable of outperforming the state of the art RSFQ SNNA, SuperNPU, by 48-99% for all benchmark NN architectures tested while occupying up to 90% less area and consuming up to nine times less power. To the best of the authors' knowledge, SHDC is currently the only superconducting ML approach feasible at practically useful scales for real-world ML tasks and capable of online learning.

This paper presents a superconducting, magnetically-coupled, shuttle-flux shift register (SF-SR) that stores single flux quantum (SFQ) pulses. This shift register has a DC bias operating margin of ±34% at 10 GHz, with a power dissipation of 3.6μ W and 38% fewer Josephson junctions (JJs) when scaled up to multiple stages compared to a data flip-flop (DFF) based shift register. The clock input is inductively coupled and is independent from the data input. We then present three applications for our SF-SR. In the first application, we add two non-destructive readout (NDRO) cells to construct a buffer that temporarily stores the temporal information of a series of race logic (RL) pulses. The second application is a pseudo-random number generator based on a linear function shift register (LFSR). The third application is N parallel SF-SRs that can act similar to a deserializer or instead can emulate a single SF-SR of N times higher clock frequency. These three applications motivate deep shift registers with many shifting intervals, which our SF-SR can implement with fewer JJs and lower power consumption compared to DFF-based shift registers.

Superconducting technology is a prime candidate for the future of computing. However, current superconducting prototypes are limited to small-scale examples due to stringent area constraints and complex architectures inspired from voltage-level encoding in CMOS; this is at odds with the ps-wide Single Quantum Flux (SFQ) pulses used in superconductors to carry information. In this work, we propose a wave-pipelined Unary SFQ (U-SFQ) architecture that leverages the advantages of two data representations: pulse-streams and Race Logic (RL). We introduce novel building blocks such as multipliers, adders, and memory cells, which leverage the natural properties of SFQ pulses to mitigate area constraints. We then design and simulate three popular hardware accelerators: i) a Processing Element (PE), typically used in spatial architectures; ii) A dot-product-unit (DPU), one of the most popular accelerators in artificial neural networks and digital signal processing (DSP); and iii) A Finite Impulse Response (FIR) filter, a popular and computationally demanding DSP accelerator. The proposed U-SFQ building blocks require up to 200× fewer JJs compared to their SFQ binary counterparts, exposing an area-delay trade-off. This work mitigates the stringent area constraints of superconducting technology.

This paper presents a superconducting magnetically coupled shift buffer based on a shuttle-flux shift register that stores single flux quantum (SFQ) pulses. The shift register has a DC bias operating margin of ±34% at 10 GHz, the power dissipation of 3.6μW at the clock bias, and 38% fewer Josephson junctions for 1024 stages compared to DFF-based shift registers. Clock bias is independent of the input pulse sequence through inductive coupling with a minimal current drive. Based on our shift register, we add two non-destructive readouts (NDRO) cells to construct a buffer that can inexpensively store the temporal information of race logic (RL) pulses or a pulse train for spiking neural networks. These applications motivate deep shift registers with many shifting intervals, which our shift register can implement with only a pair of coupled inductors and one JJ per shifting interval.