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Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this “stacked via” approach is Ni/TiN/W. We demonstrate that the second “stacked Via” is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm µm.

The metal-graphene contact resistance is one of the major limiting factors toward the technological exploitation of graphene in electronic devices and sensors. High contact resistance can be detrimental to device performance and spoil the intrinsic great properties of graphene. In this paper, we fabricate back-gate graphene field-effect transistors with different geometries to study the contact and channel resistance as well as the carrier mobility as a function of gate voltage and temperature. We apply the transfer length method and the y-function method showing that the two approaches can complement each other to evaluate the contact resistance and prevent artifacts in the estimation of carrier mobility dependence on the gate-voltage. We find that the gate voltage modulates both the contact and the channel resistance in a similar way but does not change the carrier mobility. We also show that raising the temperature lowers the carrier mobility, has a negligible effect on the contact resistance, and can induce a transition from a semiconducting to a metallic behavior of the graphene sheet resistance, depending on the applied gate voltage. Finally, we show that eliminating the detrimental effects of the contact resistance on the transistor channel current almost doubles the carrier field-effect mobility and that a competitive contact resistance as low as 700 Ω·μm can be achieved by the zig-zag shaping of the Ni contact.

In this paper, wafer level transfer of graphene on to a dielectric substrate is demonstrated based on SiO 2 -SiO 2 fusion bonding and de-bonding processes. The developed technique allows to transfer graphene on 200 mm wafer without any contamination; thus CMOS compatible. The experimental data verifies the successful transfer of the graphene on to another substrate with high quality and a yield value of 98% with average 3.5 kΩ/□ sheet resistance. To the best of authors knowledge, it is the first time demonstration of the graphene transfer based on SiO 2 -SiO 2 fusion bonding and de-bonding process on 200 mm wafer level which would allow a complete integration of graphene material into a CMOS line and opens the way for new devices based on graphene material.

We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call Graphene Base Transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 50.000., Comment: 18 pages, 6 figures

Today, electronics are implemented on rigid substrates. However, many objects in daily-life are not rigid — they are bendable, stretchable and even foldable. Examples are paper, tapes, our body, our skin and textiles. Until today there is a big gap between electronics and bendable daily-life items. Concerning this matter, the DFG Priority Program FFlexCom aims at paving the way for a novel research area: Wireless communication systems fully integrated on an ultra-thin, bendable and flexible piece of plastic or paper. The Program encompasses 13 projects led by 25 professors. By flexibility we refer to mechanical flexibility, which can come in flavors of bendability, foldability and, stretchability. In the last years the speed of flexible devices has massively been improved. However, to enable functional flexible systems and operation frequencies up to the sub-GHz range, the speed of flexible devices must still be increased by several orders of magnitude requiring novel system and circuit architectures, component concepts, technologies and materials.

Good quality, complementary-metal-oxide-semiconductor (CMOS) technology compatible, 200 mm graphene was obtained on Ge(001)/Si(001) wafers in this work. Chemical vapor depositions were carried out at the deposition temperatures of 885 °C using CH4 as carbon source on epitaxial Ge(100) layers, which were grown on Si(100), prior to the graphene synthesis. Graphene layer with the 2D/G ratio ∼3 and low D mode (i.e., low concentration of defects) was measured over the entire 200 mm wafer by Raman spectroscopy. A typical full-width-at-half-maximum value of 39 cm-1 was extracted for the 2D mode, further indicating that graphene of good structural quality was produced. The study also revealed that the lack of interfacial oxide correlates with superior properties of graphene. In order to evaluate electrical properties of graphene, its 2 × 2 cm2 pieces were transferred onto SiO2/Si substrates from Ge/Si wafers. The extracted sheet resistance and mobility values of transferred graphene layers were ∼1500 ± 100 Ω/sq and μ ≈ 400 ± 20 cm2/V s, respectively. The transferred graphene was free of metallic contaminations or mechanical damage. On the basis of results of DFT calculations, we attribute the high structural quality of graphene grown by CVD on Ge to hydrogen-induced reduction of nucleation probability, explain the appearance of graphene-induced facets on Ge(001) as a kinetic effect caused by surface step pinning at linear graphene nuclei, and clarify the orientation of graphene domains on Ge(001) as resulting from good lattice matching between Ge(001) and graphene nucleated on such nuclei.

The epitaxial integration of highly heterogeneous material systems with silicon (Si) is a central topic in (opto-)electronics owing to device applications. InP could open new avenues for the realization of novel devices such as high-mobility transistors in next-generation CMOS or efficient lasers in Si photonics circuitry. However, the InP/Si heteroepitaxy is highly challenging due to the lattice (∼8%), thermal expansion mismatch (∼84%), and the different lattice symmetries. Here, we demonstrate the growth of InP nanocrystals showing high structural quality and excellent optoelectronic properties on Si. Our CMOS-compatible innovative approach exploits the selective epitaxy of InP nanocrystals on Si nanometric seeds obtained by the opening of lattice-arranged Si nanotips embedded in a SiO2 matrix. A graphene/InP/Si-tip heterostructure was realized on obtained materials, revealing rectifying behavior and promising photodetection. This work presents a significant advance toward the monolithic integration of graphene/III-V based hybrid devices onto the mainstream Si technology platform.

We investigate the use of perfluorodecyltrichlorosilane-based self-assembled monolayer as seeding layer for chemical vapour deposition of HfO2 on large area CVD graphene. The deposition and evolution of the FDTS-based seed layer is investigated by X-ray photoelectron spectroscopy, Auger electron spectroscopy, and transmission electron microscopy. Crystalline quality of graphene transferred from Cu is monitored during formation of the seed layer as well as the HfO2 growth using Raman spectroscopy. We demonstrate that FDTS-based seed layer significantly improves nucleation of HfO2 layers so that graphene can be coated in a conformal way with HfO2 layers as thin as 10 nm. Proof-of-concept experiments on 200 mm wafers presented here validate applicability of the proposed approach to wafer scale graphene device fabrication.

The successful integration of graphene into microelectronic devices is strongly dependent on the availability of direct deposition processes, which can provide uniform, large area and high quality graphene on nonmetallic substrates. As of today the dominant technology is based on Si and obtaining graphene with Si is treated as the most advantageous solution. However, the formation of carbide during the growth process makes manufacturing graphene on Si wafers extremely challenging. To overcome these difficulties and reach the set goals, we proposed growth of high quality graphene layers by the CVD method on Ge(100)/Si(100) wafers. In addition, a stochastic model was applied in order to describe the graphene growth process on the Ge(100)/Si(100) substrate and to determine the direction of further processes. As a result, high quality graphene was grown, which was proved by Raman spectroscopy results, showing uniform monolayer films with FWHM of the 2D band of 32 cm−1.

Fabrication of graphene devices is often hindered by incompatibility between the silicon technology and the methods of graphene growth. Exfoliation from graphite yields excellent films but is good mainly for research. Graphene grown on metal has a technological potential but requires mechanical transfer. Growth by SiC decomposition requires a temperature budget exceeding the technological limits. These issues could be circumvented by growing graphene directly on insulator, implying Van der Waals growth. During growth, the insulator acts as a support defining the growth plane. In the device, it insulates graphene from the Si substrate. We demonstrate planar growth of graphene on mica surface. This was achieved by molecular beam deposition above 600°C. High resolution Raman scans illustrate the effect of growth parameters and substrate topography on the film perfection. Ab initio calculations suggest a growth model. Data analysis highlights the competition between nucleation at surface steps and flat surface. As a proof of concept, we show the evidence of electric field effect in a transistor with a directly grown channel.

Thin layers of SrHfO3, BaHfO3 and BaZrO3 are deposited onto TiN substrates and investigated in view of memory capacitor applications. The as deposited layers are amorphous and show dielectric constants of about 20. Rapid thermal annealing induces crystallization in the cubic perovskite phase and results in an increase of the dielectric constant up to 45. A combination of X-ray absorption spectroscopy (XAS) and photoemission spectroscopy measurements reports high electronic band gap values comparable with that of reference HfO2 layers.

Process compatible high- k dielectric thin films are one of the key solutions to develop high performance metal–insulator–metal (MIM) structures for future microelectronic devices. Engineered cerium–aluminate (Ce x Al 2– x O 3 ) thin films were deposited on titanium nitride metal electrodes by electron-beam co-evaporation of ceria and alumina in a molecular beam deposition chamber. X-ray photoelectron spectroscopy clearly reveals that Ce cations can be stabilized in the 3+ valence state in Ce x Al 2– x O 3 up to x = 0.7 by accommodation in the alumina host matrix. Higher Ce content was observed to result in cerium dioxide segregation in cerium aluminate matrix, probably due to the chemical tendency of Ce cations to exist rather in the 4+ than in the 3+ state. Electrical characterization of the X-ray amorphous Ce 0.7 Al 1.3 O 3 films reveals a dielectric constant value of about 11 and leakage current lower than 10 −4 A/cm 2 . No parasitic low- k interface formation between the high- k Ce 0.7 Al 1.3 O 3 film and the TiN metal electrode is detected.

We discuss the role of defects in metal oxides (mostly in strontium hafnate, barium hafnate and barium zirconate). The discussion is based on macroscopic and microscopic (C-AFM) electrical meas-urements, ab initio calculations for formation energies and elec-tronic structure of defects, numerical simulations of trap-assisted leakage, and on additional data provided by SIMS and X-ray tech-niques. We argue that moisture may be a hazardous contaminant.

We apply molecular beam epitaxy to grow GeSn-nanoparticles on top of Si-nanopillars patterned onto p-type Si wafers. We use X-ray photoelectron spectroscopy to confirm a metallic behavior of the nanoparticle surface due to partial Sn segregation as well as the presence of a superficial Ge oxide. We report the observation of stable field emission current from the GeSn-nanoparticles. We prove that field emission can be enhanced by preventing GeSn nanoparticles oxidation or by breaking the oxide layer through electrical stress. Finally, we show that GeSn/p-Si junctions have a rectifying behavior., Comment: Research paper. 7 pages, 4 figures

We demonstrate tunable Schottky barrier height and record photo-responsivity in a new-concept device made of a single-layer CVD graphene transferred onto a matrix of nanotips patterned on n-type Si wafer. The original layout, where nano-sized graphene/Si heterojunctions alternate to graphene areas exposed to the electric field of the Si substrate, which acts both as diode cathode and transistor gate, results in a two-terminal barristor with single-bias control of the Schottky barrier. The nanotip patterning favors light absorption, and the enhancement of the electric field at the tip apex improves photo-charge separation and enables internal gain by impact ionization. These features render the device a photodetector with responsivity (3 A/W for white LED light at 3 mW/cm2 intensity) almost an order of magnitude higher than commercial photodiodes. We extensively characterize the voltage and the temperature dependence of the device parameters and prove that the multi-junction approach does not add extra-inhomogeneity to the Schottky barrier height distribution. This work represents a significant advance in the realization of graphene/Si Schottky devices for optoelectronic applications., Comment: Research paper, 22 pages, 7 figures

Dislocation networks are one of the most principle sources deteriorating the performances of devices based on lattice-mismatched heteroepitaxial systems. We demonstrate here a technique enabling fully coherent germanium (Ge) islands selectively grown on nanotip-patterned Si(001) substrates. The silicon (Si)-tip-patterned substrate, fabricated by complementary metal oxide semiconductor compatible nanotechnology, features ∼50-nm-wide Si areas emerging from a SiO2 matrix and arranged in an ordered lattice. Molecular beam epitaxy growths result in Ge nanoislands with high selectivity and having homogeneous shape and size. The ∼850 °C growth temperature required for ensuring selective growth has been shown to lead to the formation of Ge islands of high crystalline quality without extensive Si intermixing (with 91 atom % Ge). Nanotip-patterned wafers result in geometric, kinetic-diffusion-barrier intermixing hindrance, confining the major intermixing to the pedestal region of Ge islands, where kinetic diffusion barriers are, however, high. Theoretical calculations suggest that the thin Si/Ge layer at the interface plays, nevertheless, a significant role in realizing our fully coherent Ge nanoislands free from extended defects especially dislocations. Single-layer graphene/Ge/Si-tip Schottky junctions were fabricated, and thanks to the absence of extended defects in Ge islands, they demonstrate high-performance photodetection characteristics with responsivity of ∼45 mA W(-1) and an Ion/Ioff ratio of ∼10(3).

Graphene electronics is expected to complement the conventional Si technologies. Graphene processing should thus be compatible with the mainstream Si technology: CMOS. Ideally, it should be possible to grow graphene directly on a Si wafer, but this does not work. Large area graphene can be grown on Cu or on Ni, its transfer to silicon must then follow, which is problematic. Researchers try therefore to grow graphene on CMOS compatible substrates, such as on Ge/Si(001) wafers. Ab initio modeling, particularly when used in combination with experimental data, can elucidate the mechanisms that govern the process of nucleation and growth of graphene, and thus provide assistance in the design of experiments and production processes. We overview our results in this context, startig from atomic C deposited on (chemically inert) graphene, through the similar cases of Si deposited on graphene and C deposited on hexagonal boron nitride, and the case of carbon on a non-inert insulator (SiO2-like surface of mica), up to C atoms and hydrocarbon molecules building graphene on Ge(001) surfaces.

Graphene has been considered for a variety of applications including novel nanoelectronic device concepts. However, the deposition of ultra-thin high-k dielectrics on top of graphene has still been challenging due to graphene's lack of dangling bonds. The formation of large islands and leaky films has been observed resulting from a much delayed growth initiation. In order to address this issue, we tested a pre-treatment with NF 3 instead of XeF 2 on CVD graphene as well as epitaxial graphene monolayers prior to the Atomic Layer Deposition (ALD) of Al 2 O 3 . All experiments were conducted in vacuo; i. e. the pristine graphene samples were exposed to NF 3 in the same reactor immediately before applying 30 (TMA-H 2 O) ALD cycles and the samples were transferred between the ALD reactor and a surface analysis unit under high vacuum conditions. The ALD growth initiation was observed by in-situ real-time Spectroscopic Ellipsometry (irtSE) with a sampling rate above 1 Hz. The total amount of Al 2 O 3 material deposited by the applied 30 ALD cycles was cross-checked by in-vacuo X-ray Photoelectron Spectroscopy (XPS). The Al 2 O 3 morphology was determined by Atomic Force Microscopy (AFM). The presence of graphene and its defect status was examined by in-vacuo XPS and Raman Spectroscopy before and after the coating procedure, respectively.

Integration of graphene with Si microelectronics is very appealing by offering potentially a broad range of new functionalities. New materials to be integrated with Si platform must conform to stringent purity standards. Here, we investigate graphene layers grown on copper foils by chemical vapor deposition and transferred to silicon wafers by wet etch and electrochemical delamination methods with respect to residual sub-monolayer metallic contaminations. Regardless of the transfer method and associated cleaning scheme, time-of-flight secondary ion mass spectrometry and total reflection x-ray fluorescence measurements indicate that the graphene sheets are contaminated with residual metals (copper, iron) with a concentration exceeding 10$^{13}$ atoms/cm$^{2}$. These metal impurities appear to be partly mobile upon thermal treatment as shown by depth profiling and reduction of the minority charge carrier diffusion length in the silicon substrate. As residual metallic impurities can significantly alter electronic and electrochemical properties of graphene and can severely impede the process of integration with silicon microelectronics these results reveal that further progress in synthesis, handling, and cleaning of graphene is required on the way to its advanced electronic and optoelectronic applications., 26 pages, including supporting information

We fabricate back-gated field effect transistors using Niobium electrodes on mechanically exfoliated monolayer graphene and perform electrical characterization in the pressure range from atmospheric down to 10-4 mbar. We study the effect of room temperature vacuum degassing and report asymmetric transfer characteristics with a resistance plateau in the n-branch. We show that weakly chemisorbed Nb acts as p-dopant on graphene and explain the transistor characteristics by Nb/graphene interaction with unpinned Fermi level at the interface., Comment: 10 pages, Research Paper

We propose a hybrid device consisting of a graphene/silicon (Gr/Si) Schottky diode in parallel with a Gr/SiO2/Si capacitor for high-performance photodetection. The device, fabricated by transfer of commercial graphene on low-doped n-type Si substrate, achieves a photoresponse as high as 3 AW^(-1) and a normalized detectivity higher than 3.5 10^12 cmHz^(1/2) W^(-1) in the visible range. The device exhibits a photocurrent exceeding the forward current, because photo-generated minority carriers, accumulated at Si/SiO2 interface of the Gr/SiO2/Si capacitor, diffuse to the Gr/Si junction. We show that the same mechanism, when due to thermally generated carriers, although usually neglected or disregarded, causes the increased leakage often measured in Gr/Si heterojunctions. At room temperature, we measure a zero-bias Schottky barrier height of 0.52 eV, as well as an effective Richardson constant A**=4 10^(-5) Acm^(-2) K^(-2) and an ideality factor n=3.6, explained by a thin (< 1nm) oxide layer at the Gr/Si interface., Research paper. 26 pages, 8 figures

Physical vapor deposition of Si onto transferred graphene is investigated. At elevated temperatures, Si nucleates preferably on wrinkles and multilayer graphene islands. In some cases, however, Si can be quasi-selectively grown only on the monolayer graphene regions while the multilayer islands remain uncovered. Experimental insights and ab initio calculations show that variations in the removal efficiency of carbon residuals after the transfer process can be responsible for this behavior. Low-temperature Si seed layer results in improved wetting and enables homogeneous growth. This is an important step towards realization of electronic devices in which graphene is embedded between two Si layers., Comment: 5 pages, 6 figures

Among the many anticipated applications of graphene, some - such as transistors for Si microelectronics - would greatly benefit from the possibility to deposit graphene directly on a semiconductor grown on a Si wafer. We report that Ge(001) layers on Si(001) wafers can be uniformly covered with graphene at temperatures between 800{\deg}C and the melting temperature of Ge. The graphene is closed, with sheet resistivity strongly decreasing with growth temperature, weakly decreasing with the amount of deposited C, and reaching down to 2 kOhm/sq. Activation energy of surface roughness is low (about 0.66 eV) and constant throughout the range of temperatures in which graphene is formed. Density functional theory calculations indicate that the major physical processes affecting the growth are: (1) substitution of Ge in surface dimers by C, (2) interaction between C clusters and Ge monomers, and (3) formation of chemical bonds between graphene edge and Ge(001), and that the processes 1 and 2 are surpassed by CH$_{2}$ surface diffusion when the C atoms are delivered from CH$_{4}$. The results of this study indicate that graphene can be produced directly at the active region of the transistor in a process compatible with the Si technology.

In this work, we propose an integration approach for double gate graphene field effect transis- tors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The com- plete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bend- ing in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Despite exceptional intrinsic properties of graphene, field effect transistors with graphene channels (GFETs) are limited by the absence of an electronic band gap. The resulting low ION-IOFF ratio and low output resistance makes GFETs unsuitable for logic applications [1] and limits radio frequency (RF) applications [2]. We will present a graphene-based electronic device in which the 0 eV band gap does not limit the device performance: a hot electron transistor (HET) with a graphene base (Graphene Base Transistor, GBT) [3,4]. The single-atomic thinness and high conductivity are decisive advantages of a graphene base [5]. Here, we report on the fabrication and full DC-characterization of GBTs with high ION-IOFF ratio of 105.

Defects in form of dislocations at the interface and threading arms in the film as well as SiGe intermixing are the main mechanisms to release the crystallographic misfit strain in Germanium (Ge) heterostructures grown on the mature Silicon (Si) wafer platform, severely deteriorating thereby the superior optoelectronic properties of Ge for device applications. We demonstrate here a novel technique, enabling fully coherent, high Ge content islands on nano-tip patterned Si (001) substrates by the suppression of plastic relaxation as well as SiGe intermixing. The Si-tip patterned substrate, fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology, features ~50 nm wide Si tips emerging from a SiO2 matrix and arranged in an ordered lattice. Molecular beam epitaxy (MBE) growths result in Ge nano-islands with high selectivity and having homogeneous shape and size. The ~850°C growth temperature required for ensuring selective growth has been shown to lead to the formation of Ge islands of high crystalline quality without extensive Si intermixing (with 91 at.% Ge). Nano-tip patterned wafers result in geometric, kinetic diffusion barrier intermixing hindrance (in particular surface diffusion suppression) confining the major intermixing to the pedestal region of Ge islands where kinetic diffusion barriers are however high. Theoretical calculations suggest that the self-assembled thin SiGe layer at the interface plays nevertheless a significant role in realizing fully coherent Ge nano-islands free from extended defects especially dislocations. Finally, single layer graphene (SLG)/Ge/Si-tip Schottky junctions were fabricated and thanks to the absence of extended defects and SiGe intermixing in the Ge islands, high performance photodetection characteristics with responsivity and Ion/Ioff ratio of ~45 mA/W and ~103, respectively, are demonstrated.

We study the contact resistance and the transfer characteristics of back-gated field effect transistors of mono- and bi-layer graphene. We measure specific contact resistivity of ~ 7 k Ω μm 2 and ~ 30k Ω μm 2 for Ni and Ti, respectively. We show that the contact resistance is a significant contributor to the total source-to-drain resistance and it is modulated by the back-gate voltage. We measure transfer characteristics showing a double dip feature that we explain as the effect of doping due to charge transfer from the contacts causing minimum density of states for graphene under the contacts and in the channel at different gate voltage.

We present a novel, graphene-based device concept for high-frequency operation: a hot electron graphene base transistor (GBT). Simulations show that GBTs have high current on/off ratios and high current gain. Simulations and small-signal models indicate that it potentially allows THz operation. Based on energy band considerations we propose a specific materials solution that is compatible with SiGe process lines., 9 pages, 3 figures; IEEE Electron Device Letters, Vol.33, Issue 5, (2012)

We report the observation and characterization of field emission current from individual single- and few-layer graphene flakes laid on a flat SiO2/Si substrate. Measurements were performed in a scanning electron microscope chamber equipped with nanoprobes, used as electrodes to realize local measurements of the field emission current. We achieved field emission currents up to 1 {\mu}A from the flat part of graphene flakes at applied fields of few hundred V/{\mu}m. We found that emission process is stable over a period of several hours and that it is well described by a Fowler-Nordheim model for currents over 5 orders of magnitude.

We discuss the origin of an additional dip other than the charge neutrality point observed in the transfer characteristics of graphene-based field-effect transistors with a Si/SiO2 substrate used as the back-gate. The double dip is proved to arise from charge transfer between the graphene and the metal electrodes, while charge storage at the graphene/SiO2 interface can make it more evident. Considering a different Fermi energy from the neutrality point along the channel and partial charge pinning at the contacts, we propose a model which explains all the features observed in the gate voltage loops. We finally show that the double dip enhanced hysteresis in the transfer characteristics can be exploited to realize graphene-based memory devices.

Extending the scalability of deep trench capacitor dynamic random access memories requires introduction of a high-k dielectric-based storage capacitor structure. Pr-enriched Al2O3 dielectrics with TiN electrodes appear as a promising materials system for this application. Electrical measurements performed on this materials combination show, however, that achieving a very low capacitance equivalent thickness and low leakage current requires very careful control of the electrode/dielectric interface properties. In particular, formation of a parasitic interface layer has to be avoided. For this purpose, we carried out a systematic synchrotron radiation x-ray photoelectron spectroscopy study to non-destructively investigate the interface reactivity of the PrxAl2-xO3 (x = 0, 1, 2)dielectrics with TiN metal electrodes. The depth profiling study shows that the TiN substrate is covered with a native TiO2. Additionally, a thin interfacial Ti oxynitride layer is present between these compounds, resulting in a TiN/TiNO/TiO2 materials stack. Molecular beam deposition of Al2O3 onto substrates of this structure leads to a remarkable reduction of the native oxide. In contrast, in the same way deposited PrAlO3 and Pr2O3 dielectrics are significantly less reactive towards TiO2. As a consequence, the native TiON/TiO2 remains the main component of the interface layer in the TiN/PrAlO3 and TiN/Pr2O3 capacitor stacks. Such a configuration poses severe scalability problems to the Pr aluminate dielectrics.

Chemical vapor deposition (CVD) was applied to grow dielectric HfO2 layers on graphene/SiO2/Si and graphene/TiN/Si reference substrates directly, i.e., without a seed layer or any other functionalization of graphene. It was found that the presence of bilayer and (generally) multilayer graphene islands on nominally monolayer graphene strongly impacts the nucleation and the growth of HfO2. No damage inflicted by the CVD process on the graphene could be detected by Raman spectroscopy. According to x-ray diffraction, the films, grown on graphene at 400 °C and having thickness between 5 and 50 nm, were polycrystalline. Electrical measurements were performed for metal–insulator–metal (MIM) capacitors produced by evaporating Au and TiN top electrodes on the HfO2 film. Leakage currents were in the range of 10−8 A/cm2 at 1 V for 50 nm HfO2 grown on graphene, exceeding by one order of magnitude the currents measured for the reference HfO2/TiN MIM structures. The films grown on graphene have a dielectric constant of...

We investigate a seed layer-free growth of HfO2 on commercially available chemical vapor deposited (CVD) graphene from various suppliers. It is revealed that the samples of monolayer graphene transferred from Cu to SiO2/Si substrates have different coverage with bi- and multi-layer graphene islands. We find that the distribution and number of such islands impact the nucleation and growth of HfO2 by CVD. In particular, we show that the edges and surface of densely distributed bi-layer graphene islands provide good nucleation sites for conformal CVD HfO2 layers. Dielectric constant of 16 is extracted from measurements on graphene-HfO2-TiN capacitors.

Controlled substitution of Hf4+ by Ti4+ ions in thin BaHfO3 was investigated in view of future dynamic random access memory (DRAM) applications. The 50% substitution of Hf ions reduces the crystallization temperature by about 200 °C with respect to BaHfO3 layers making the BaHf0.5Ti0.5O3 layers compatible with DRAM processing. The resulting cubic BaHf0.5Ti0.5O3 dielectrics show k∼90 after rapid thermal annealing at 700 °C which is three times higher than for BaHfO3 at similar temperatures. Leakage current values of 4×10−5 A/cm2 at 0.5 V for Pt/BaHf0.5Ti0.5O3/TiN capacitors with capacitance equivalent thickness

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Praseodymium (Pr) silicate dielectric layers were prepared by oxidation and subsequent N2 annealing of thin Pr metal layers on SiO2∕Si(100) substrates. Transmission electron microscopy studies reveal that the resulting dielectric has a bilayer structure. Nondestructive depth profiling by using synchrotron radiation x-ray photoelectron spectroscopy shows that, starting from the substrate, the dielectric stack is composed of a SiO2-rich and a SiO2-poor Pr silicate phase. Valence and conduction band offsets of about 2.9 and 1.6eV, respectively, between the dielectric and the Si(100) substrate bands were deduced. Pr silicate films with an equivalent oxide thickness of 1.8nm show approximately three orders of magnitude lower leakage currents than silicon oxynitride references. Capacitance versus voltage measurements of the Pr silicate/Si(100) system report a flat band voltage shift of 0.22V, an effective dielectric constant of about 11 and a reasonably good interface quality with an interface state density on ...