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A combined X-ray photon correlation spectroscopy and rheology study is carried out to capture the evolution of structure, fast particle-scale dynamics, and moduli (elastic and loss) at early times of gel formation near the fluid–gel boundary of a suspension of nanoparticles. The system is comprised of moderately concentrated suspensions of octadecyl silica in decalin (ϕ = 0.2) undergoing thermoreversible gelation. Near the gel boundary, the rate of gel formation is very sensitive to changes in attraction strength. However, we find that at different attraction strengths, the system goes through identical intermediate states of microscopic and macroscopic behavior, even though the absolute time needed to form a gel varies by orders of magnitude. We identify a single dimensionless time parameter, tw/tg, where tw is the wait time following the quench and tg is the rheologically determined gel time, that captures the similarity in gel formation at a range of attraction strengths. Following a temperature quench below the gel boundary, the system is initially fluidlike and forms diffusive clusters (∼8.5 times the particle diameter). After a lag-time, tL, clusters aggregate to form a network like structure which is characterized by the onset of mechanical rigidity and a rapid growth in microscopic relaxation times. At tg, the Baxter parameter obtained from adhesive hard sphere fits of the structure factor attains a constant value corresponding to the theoretical percolation boundary, thus demonstrating that gelation is percolation driven. [ABSTRACT FROM AUTHOR]

We report on the performance of a low noise and high count rate readout ASIC with binary architecture and energy window selection for X-ray imaging applications using semiconductor detectors. The ASIC called RG64 is designed in 0.35 [micro]m CMOS process and its total area is 3900 x 5000 [micro][m.sup.2]. The core of RG64 consists of 64 readout channels. Each channel is built of a charge sensitive amplifier with a second order shaper of peaking time 75 ns, two independent discriminators with an 8-bit offset correction circuit and two independent 20-bit counters with RAM memory buffers. The ENC of the circuit reaches the value of about 126 el. rms with 1 pF input load and 5 mW power consumption per single channel. The mean gain in the multichannel ASIC is about 50 [micro]V/el., with the dispersion from channel to channel of 0.9% (on one sigma level). The deviation of the effective threshold voltage spread for given energy can be reduced to less than 7 el. rms (calculated to the charge sensitive amplifier input). High count rate measurements have been performed up to 2 Mcps of average rate of input pulses, both for AC and DC coupled silicon strip detectors with X-ray photons of energy 8.04 keV. The RG64 can operate both in the continuous readout mode and in the readout mode separate from exposure. Index Terms--Low-noise electronics, mixed signal circuits.

Modern X-ray imaging systems require low noise high-count-rate multichannel front-end electronics. Such systems widely use charge-sensitive amplifiers (CSA) with pole-zero cancellation (PZC) circuits for sensor readout. CSAs in multichannel ASICs often include continuous reset systems based on MOS transistors discharging the integrating capacitance. Noise requirements for such front-end electronics put the effective CSA feedback resistance in the range of hundreds of M[ohm]. On the other hand, the high input pulse rate generates adc voltage shift at the CSA output that modifies the CSA feedback resistance and degrades the PZC circuit performance. In the paper we analyze these problems and propose a novel circuit solution to bias transistors in the CSA feedback and in the PZC circuit. This bias circuit tracks the above mentioned voltage shift at the CSA output and ensures proper cancellation of the CSA feedback pole even in the case of high rates of input pulses. We present measurements of a test structure for the continuous CSA feedback discharge and implementation of this circuit in a fast multichannel ASIC manufactured in the 0.35 [micro]m CMOS technology. The circuit performance for the high input pulse rate is described in detail. Index Terms--Charge sensitive amplifier, pole-zero cancellation circuit, pulse pile-up.

We present the measurements of matching and high count rate performance of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 [micro]m CMOS process and its total area is 3900 x 5000 [micro][m.sup.2]. The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures a low spread of discriminator effective threshold, namely 0.4 mV at one sigma level. The mean gain in the multichannel ASIC is 54 [micro]V/el, with a good uniformity from channel-to-channel (sd/mean [approximately equal to] 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz average rate of input signals. Index Terms--Charge sensitive amplifier, count rate, matching.

The paper describes the development of a multi-channel readout system for X-ray measurements using silicon strip detectors. The system comprises two application-specific integrated circuits (ASICs), a front-end chip, and a digital data storage chip. In the front-end ASIC, a binary readout scheme is employed. The binary data are stored in the asynchronous counters and read out serially at the end of the measurement sequence. The front-end circuit is designed such that it can work with direct current coupled detectors with a leakage current up to few nanoamperes. The size of the input device is optimized for a detector capacitance in the range from 2-5 pF per strip. An equivalent noise charge of 110 electrons [micro]s has been achieved for the total strip capacitance of 2.5 pF at the peaking time of 1 [micro]s. Low noise performance and high counting-rate capability have been demonstrated by measurements of X-ray spectra. Index Terms--Front-end electronics, low-noise electronics, silicon strip detectors, X-ray detection.