1,396 results on '"Groeseneken, G."'
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2. Variability in Planar FeFETs—Channel Percolation Impact
3. Upcoming Challenges of ESD Reliability in DTCO with BS-PDN Routing via BPRs
4. Recent Trends in Bias Temperature Instability
5. The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits
6. Stack optimization of oxide-based RRAM for fast write speed (
7. Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study
8. Comprehensive Investigations of HBM ESD Robustness for GaN-on-Si RF HEMTs
9. IMPACT OF HIGH-κ PROPERTIES ON MOSFET ELECTRICAL CHARACTERISTICS
10. Scaled X-bar TiN/HfO2/TiN RRAM cells processed with optimized plasma enhanced atomic layer deposition (PEALD) for TiN electrode
11. Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs
12. Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO
13. Gate current random telegraph noise and single defect conduction
14. Statistical insight into controlled forming and forming free stacks for HfOx RRAM
15. Analytical model for anomalous Positive Bias Temperature Instability in La-based HfO2 nFETs based on independent characterization of charging components
16. Towards understanding hole traps and NBTI of Ge/GeO2/Al2O3 structure
17. Superior reliability of high mobility (Si)Ge channel pMOSFETs
18. Towards CMOS-compatible single-walled carbon nanotube resonators
19. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks
20. Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs
21. A comprehensive study of channel hot-carrier degradation in short channel MOSFETs with high-k dielectrics
22. Dielectrophoretic assembly of suspended single-walled carbon nanotubes
23. Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs
24. Drive current enhancement in p-tunnel FETs by optimization of the process conditions
25. Temperature and voltage dependences of the capture and emission times of individual traps in high-k dielectrics
26. On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si 0.45Ge 0.55 pMOSFETs
27. ESD HBM Discharge Model in RF GaN-on-Si (MIS)HEMTs
28. Hot-Carrier Degradation During Dynamic Stress
29. The Mechanisms of Hot-Carrier Degradation
30. Detailed analysis of charge pumping and IdVg hysteresis for profiling traps in SiO 2/HfSiO(N)
31. Channel hot-carrier degradation in pMOS and nMOS short channel transistors with high-k dielectric stack
32. Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs
33. Significant reduction of Positive Bias Temperature Instability in high-k/metal-gate nFETs by incorporation of rare earth metals
34. Recent Trends in Bias Temperature Instability
35. Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices
36. NBTI lifetime prediction and kinetics at operation bias based on ultrafast pulse measurement
37. Velocity and mobility investigation in 1-nm-EOT HfSiON on Si (110) and (100)-does the dielectric quality matter?
38. Understanding the memory window in 1T-FeFET memories: a depolarization field perspective
39. Compact Modeling of Multidomain Ferroelectric FETs: Charge Trapping, Channel Percolation, and Nucleation-Growth Domain Dynamics
40. Impact of ambient temperature on the switching of voltage-controlled perpendicular magnetic tunnel junction
41. Thermal recovery from stress-induced high-[kappa] dielectric film degradation
42. Electrical and reliability characterization of metal-gate/HfO 2/Ge FET’s with Si passivation
43. Hydrogen induced positive charge in Hf-based dielectrics
44. Performance assessment of (1 1 0) p-FET high- κ/MG: is it mobility or series resistance limited?
45. Dielectric quality and reliability of FUSI/HfSiON devices with process induced strain
46. Charge pumping spectroscopy: HfSiON defect study after substrate hot electron injection
47. A consistent model for the hard breakdown distribution including digital soft breakdown: the noble art of area scaling
48. Impact of process conditions on interface and high- κ trap density studied by variable Tcharge- Tdischarge charge pumping (VT 2CP)
49. Impact of weak Fermi-level pinning on the correct interpretation of III-V MOS C-V and G-V characteristics
50. Mobility extraction using RFCV for 80 nm MOSFET with 1 nm EOT HfSiON/TiN
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