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Press-fit technology provides an electrical and mechanical connection by inserting a press-fit pin into a through-hole of a printed circuit board (PCB). Recently, there has been a wide interest in the long-term reliability of the press-fit pin interconnect of electric systems under various thermo-mechanical conditions due to the integration and minimization of electric devices. Compared to a ball grid array (BGA) interconnection, press-fit pin connector interconnects are expected to have a different degradation mechanism. In this study, the impact factors affecting reliability and degradation mechanism of press-fit connector pins were investigated. The bonding strength of inserted pins was measured before and after thermal cycling at room temperature and elevated temperature conditions. It is observed that the bonding strength of the press-fit pins to the PCB Cu wall increased after thermal cycling. The development of an intermetallic compound between the Cu pin and the Cu wall is observed. The microstructure of the press-fit connector pin and the Cu wall and localized stress and strain levels were analyzed by electron backscattered diffraction including inverse pole figure maps, grain reference orientation deviation maps, and strain contouring maps. Along with the increase of pull strength after thermal cycling, an increase in residual stresses was observed while strain contouring maps exhibited a decrease in localized strains at the interface between a press-fit pin and copper wall of a PCB.

This paper reports experimental observations showing that a current flow produces an effect of strengthening a solder joint against a shear load. This conclusion is found from a single-joint shear test conducted on Sn–1Ag–0.5Cu wt% (SAC 105) joints with in situ current stressing varied from 700 to 1400 A/cm2 at room temperature. To isolate the current effect from the Joule heat effect, the same type of tests were conducted at room temperature, 40, 50, and 80 °C, without current applied to the joint, thus mimicking the condition of steady-state temperature resulting from Joule heating. Comparative testing was also conducted after aging the samples at 150 °C for 200 h. These tests produced indications suggesting that the current flow causes the maximum shear load to increase, while the rise in temperature by the Joule heat effect results in the opposite effect. Experimentally, as much as a 9.5% increase in the maximum shear load was observed from the isothermally aged sample tested under a current density of 700 A/cm2, while an ~ 25% reduction was estimated to result from a temperature increase by Joule heating. The potential mechanism for these observations is discussed.

Various external load conditions affecting components on electronic devices and modules are constant factors, which need to be considered for the component long-term reliability. Recently, to enhance the high stress component thermo-mechanical cycling performance, various types and configuration using edgebond and edgefill technology are introduced and tested. These applications induce a multi-axis loading condition, which alter the degradation mechanism and failure location during thermal cycling, which need closer investigation. In this study, high stress 12x12mm2 wafer level chip scale packages (WLCSP) were selected and subject to thermal cycling with full-edgebond, dot-edgebond and edgefill adhesive, which improves the characteristic lifecycle numbers base on the configurations, but altered the failure location due to different stress conditions. The -40 to 125oC thermal cycling profile revealed localized degradation per configuration during thermal cycling, showed a shift of the crack propagation path, based on full-edgebond, dot-edgebond and edgefill adhesive sample conditions. Through these series of observation, the interconnect thermal cycling degradation mechanisms are able to be explained. The correlation between the stress condition and microstructure are presented and discussed based on Electron backscattered diffraction (EBSD) analysis.

Mechanical integrity of low-k dielectric films remains a quality and reliability challenge for devices using advanced silicon nodes. In wafer fabs, while great efforts are made in controlling and monitoring individual processing steps, the overall mechanical quality of a particular device is not often effectively monitored. Defects such as interfacial delamination may only manifest themselves during system assembly processes or in-field operation, bringing significant disruption and impact onto production and product quality. As silicon sizes and package sizes continue to grow, chip-packaging interaction becomes more significant, and the risk of low-k related failures increases as a result. Particularly for 3D and 2.5D devices, the complexity of chip stacking makes it important to have a quantitative assessment of dielectric quality for both yield and ongoing reliability management purposes. The adoption of micro-Cu pillars on 2.5D and 3D devices provides an opportunity for direct measurement of integration quality. If shear testing can be performed on individual micro-Cu pillars, responses from such testing can be analyzed and quantified as a direct measurement of integration quality. Furthermore, such testing can be performed on a specific device of interest and on specific locations on a die, which makes it possible to use this technique as a product quality control method. In this paper we will report results from shear testing on sub-30 micron micro-Cu pillars. Data from multiple wafers, dies, and bump locations will be reported. Responses such as load-distance curves and maximum fracture load are analyzed. In addition, multi-level finite element models are developed to simulate the shear test. Locations of stress concentration will be identified and compared with fracture interfaces from the shear test. Responses to changes in properties of the dielectric layers will also be investigated, which provides insight into the variations in shear strength observed in real-life shar testing.

Large body-size and heterogeneously integrated packages have become essential for high-performance computing applications. As an example, designs such as silicon interposer-based 2.5D packages have enabled the integration of high-performance silicon and memory in close proximity, greatly increasing the bandwidth and throughput of these devices. Within such a package, the interaction among the many sub-components and materials creates a complex thermo-mechanical response in the interconnections, which includes micro-bumps and C4 bumps. In addition, such components frequently require a high-layer count and high-thickness PCB, which creates a challenge for the reliability of the solder joints. As a result, the overall reliability of PCB assembly needs to be evaluated at every level of the interconnect. In this study, a large 2.5D flip chip package was subject to temperature cycling testing. This component was also attached to a PCB, and the entire assembly went through temperature cycling as well. Over the duration of testing, a series of microstructure evaluations were performed at the micro-bump, C4 bump, and solder joint level. Each analysis included polarized optical imaging, SEM (Scanning Electron Microscope), EBSD (Electron Backscatter Diffraction) and strain contour analysis. With these techniques, the methodology was able to not only observe the degradation and microstructure evolution, but was also able to reveal the damage by collecting high-resolution strain / stress distribution data at critical locations such as corner bumps and solder joints. These data provided insight into metallurgical processes that alter the grain structure of solder joints at different dimensions and locations, and ultimately the details of the failure mechanisms and processes.

The mechanical stability of Sn-Ag-Cu interconnects with low and high silver content against mechanical shock at room and elevated temperatures was investigated. With a heating element-embedded printed circuit board design, a test temperature from room temperature to 80°C was established. High impact shock tests were applied to isothermally pre-conditioned ball-grid array interconnects. Under cyclic shock testing, degradation and improved shock performances were identified associated with test temperature variation and non-solder mask defined and solder-mask defined pad design configuration differences. Different crack propagation paths were observed, induced by the effect of the elevated temperature test conditions and isothermal aging pre-conditions.