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As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continues to diminish. The limitation of 1.35 NA posed by water-based lithography has led to the application of various resolution enhancement techniques (RET), for example, use of strong phase-shifting masks, aggressive OPC and sub-resolution assist features, customized illuminators, etc. The adoption of these RET techniques combined with the requirements to detect even smaller defects on masks due to increasing MEEF, poses considerable challenges for a mask inspection engineer. Inspecting masks under their actinic-aerial image conditions would detect defects that are more likely to print under those exposure conditions. However, this also makes reviewing such defects in their low-contrast aerial images very challenging. On the other hand, inspecting masks under higher resolution or mask-plane inspection optics would allow for better viewing of defects post-inspection. However, such inspections generally would also detect many more defects, including critical and nuisance, thereby making it difficult to judge which are of real concern for printability on wafer. Hence, a comprehensive approach is needed in handling defects both post-aerial and post-high resolution inspections. This paper focuses on review of defects post high resolution or mask-plane inspections, especially in the wafer-fab environment. A later paper will focus on review of defects post aerial-image inspections.

Patterning of contact hole using KrF lithography system for the sub 90nm technology node is one of the most challenging tasks. Contact hole pattern can be printed using Off-Axis Illumination(OAI) such as dipole or Quasar or Quadrupole at KrF lithography system. However this condition usually offer poor image contrast and poor Depth Of Focus(DOF), especially isolated contact hole. Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip CD variation reduction. The insertion of SRAF in a contact design is mostly done using rule based scripting. However the rule based SRAF strategy that has been followed historically is not always able to increase the process window of these 'forbidden pitches' sufficiently to allow sustainable manufacturing. Especially in case of random contact hole, rule-based SRAF placement is almost impossible task. We have used an inverse lithography technique to treat random contact hole. In this paper we proved the impact of SRAF configuration. Inverse lithography technique was successfully used to treat random contact holes. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described. As a conclusion, we suggest methodology to set up optimum SRAF configuration with rule and inverse lithography technology.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns under mask inspection optical conditions continues to diminish. Furthermore, as mask complexity and MEEF has also increased, it requires detecting even smaller defects in the already narrower pitch mask patterns. This leaves the mask inspection engineer with the option to either purchase a higher resolution mask inspection tool or increase the detector sensitivity on the existing inspection system or maybe even both. In order to meet defect sensitivity requirements in critical features of sub-32nm node designs, increasing sensitivity typically results in increased nuisance (i.e., small sub-specification) defect detection by 5-20X defects making post-inspection defect review non-manufacturable. As a solution for automatically dispositioning the increased number of nuisance and real defects detected at higher inspection sensitivity, Luminescent has successfully extended Inverse Lithography Technology (ILT) and its patented level-set methods to reconstruct the defective mask from its inspection image, and then perform simulated AIMS dispositioning on the reconstructed mask. In this technique, named Lithographic Plane Review (LPR), inspection transmitted and reflected light images of the test (i.e. defect) and reference (i.e., corresponding defect-free) regions are provided to the "inversion" engine which then computes the corresponding test and reference mask patterns. An essential input to this engine is a well calibrated model incorporating inspection tool optics, mask processing and 3D effects, and also the subsequent AIMS tool optics to be able to then simulate the aerial image impact of the defects. This flow is equivalent to doing an actual AIMS tool measurement of every defect detected during mask inspection, while at the same time maintaining inspection at high enough resolution. What makes this product usable in mask volume production is the high degree of accuracy of mask defect reconstruction, predicting actual AIMS measurements to within ±4% CD error for > 95% of defects while not missing any OOS (out-of-specification) defect and maintaining high simulation throughput of ≥250 defects/min on Luminescent's distributed computing platform. This technique enables inspection recipes to be setup based on the sensitivity required to detect small but lithographically-significant defects, even if in the process a large number of nuisance defects are detected. LPR is being implemented as an integral part of defect classification for high-volume sub-32nm technology nodes and higher. Furthermore, this technique will be essential to the lithographic disposition of defects detected on EUV masks inspected under non-actinic conditions.

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus (DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly impossible task. To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.

In this paper, an overview of Inverse Lithography Technology (ILT) based on Level Set Methods (LSM) is provided. Applications of ILT in the advanced lithography process are then shown for several different devices, including DRAM, SRAM, FLASH, random logic, and imaging devices. ILT is used to correct the main patterns, as well as automatically insert SRAFs using model-based mathematical methods. The process of SRAF generation in ILT is unified with the process of inversion. With the help of ILT, SRAFs can be inserted where physically needed, independent of source parameters or target patterns. Results that demonstrate the adaptive nature of ILT SRAF insertion capability are presented. Wafer verification results were collected by multiple advanced semiconductor manufacturing companies at advanced technology nodes, including 45nm and 32nm nodes, and compared with their current OPC solution. Final wafer results presented here demonstrate that ILT improves pattern fidelity, enlarges process window, and provides remarkable control for line-end shortening.

This paper presents the results of applying ILT to SMIC's first 65nm tape out. ILT mathematically determines the mask features that produce the desired on-wafer results for best pattern fidelity, largest process window or an desired combination of both. SMIC applied this technology to its first 65nm tape-out to study its performance and benefits for deep sub-wavelength lithography. SMIC selected 3 SRAM designs as the first set of test cases, because SRAM bit-cells contain features which are lithographically challenging. Firstly, three experiments were performed to optimize the illumination and mask design of a pair of layers by optimizing exposure energy, enabling SRAF, and enforcing mask constraints. Secondly, mask manufacturability (including fracturing and writing time) and wafer print performance of ILT was studied. Thirdly, mask patterns generated by both conventional Optical Proximity Correction (OPC) and ILT, both using only their optical models, were placed on the mask side-by-side. The results demonstrated that ILT achieved better CD accuracy and produced significantly larger process window than conventional OPC.

In an optical vortex, the wavefront spirals like a corkscrew, rather than forming planes or spheres. Since any nonzero optical amplitude must have a well-defined phase, the axis of a vortex is always dark. Printed in negative resist at 248nm and NA=0.63, 250nm pitch vortex arrays would produce contact holes with 80nm 0.6 can be patterned using a chromeless phase-edge mask composed of rectangles with nominal phases of 0°, 90°, 180° and 270°. Analytic and numerical calculations have been performed to characterize the aerial images projected from such vortex masks using the Kirchhoff-approximation and rigorous EMF methods. Combined with resist simulations, these analyses predict process windows with ≈10%Elat and >200nm DOF for 80nm CDs on pitches greater than or equal to 250nm at σ greater than or equal to 0.15. Smaller CDs and pitches are possible with shorter wavelength and larger NA while larger pitches give rise to larger CDs. At pitch >0.8μm, the vortices begin to print independently for σ greater than or equal to 0.3. Such “independent” vortices have a quasi-isofocal dose that gives rise to 100nm contacts with Elat>9% and DOF>500nm at σ=0.3. The extra darkness of the nominal 270° phase step can be accommodated by fine-tuning the etch depth. A reticle fabrication process that achieves the required alignment and vertical wall profiles has been exercised and test masks analyzed. In an actual chip design, unwanted vortices and phase step images would be erased from the resist pattern by exposing the wafer with a second, more conventional trim mask. Vortex via placement is consistent with the coarse-gridded grating design paradigms which would - if widely exercised - lower the cost of the required reticles. Compared to other ways of producing deep sub-wavelength contacts, the vortex via process requires fewer masks and reduces the overlay and process control challenges. A high resolution negative-working resist process is essential, however.

An optical vortex has a phase that spirals like a corkscrew. Since any nonzero optical amplitude must have a well-defined phase, the axis of a vortex (where the phase is undefined) is always dark. Printed in negative resist, lowest order vortices would produce contact holes with 0.2 0.6 can be produced using a chromeless phase-edge mask composed of rectangles with phases of 0°, 90°, 180° and 270°. EMF and Kirchhoff-approximation simulations reveal that the image quality of the dark spots is excellent, and predict a process window with 15% exposure latitude and 400nm DOF for 80nm diameter spots on pitches ≥250nm at σ=0.15. EMF simulations predict that the 0-270° phase step will not be excessively dark if the quartz wall is vertical. Chrome spots at the centers can control the diameters which otherwise are set by the parameters of the imaging system and exposure dose. Unwanted vortices can be erased from the image by exposing with a second, more conventional, trim mask. This method would be superior to the other ways of producing sub-wavelength vias, but successful implementation requires the development of appropriate negative-tone resist processes.