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Your search keyword '"Goutis, C. E."' showing total 49 results
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49 results on '"Goutis, C. E."'

1. A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms

Author

Galanis, M. D., Milidonis, A., Theodoridis, G., Soudris, D., and Goutis, C. E.

Subjects
Computer Science - Hardware Architecture
Abstract

In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hybrid reconfigurable architecture is considered so as the methodology can be applicable to a large number of heterogeneous reconfigurable platforms. The methodology mainly consists of two stages, the analysis and the mapping of the application onto fine and coarse-grain hardware resources. A prototype framework consisting of analysis, partitioning and mapping tools has been also developed. For the coarse-grain reconfigurable hardware, we use our previous-developed high-performance coarse-grain data-path. In this work, the methodology is validated using two real-world applications, an OFDM transmitter and a JPEG encoder. In the case of the OFDM transmitter, a maximum clock cycles decrease of 82% relative to the ones in an all fine-grain mapping solution is achieved. The corresponding performance improvement for the JPEG is 43%., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Published
2007

2. Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path

Author

Galanis, M. D., Theodoridis, G., Tragoudas, S., Soudris, D., Goutis, C. E., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Macii, Enrico, editor, Paliouras, Vassilis, editor, and Koufopavlou, Odysseas, editor

Published
2004
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3. Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Author

Galanis, M. D., Theodoridis, G., Tragoudas, S., Soudris, D., Goutis, C. E., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Becker, Jürgen, editor, Platzner, Marco, editor, and Vernalde, Serge, editor

Published
2004
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37. Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse.

Author

Milidonis, A., Porpodas, V., Alachiotis, N., Kakarountas, A. P., Michail, H., Panagiotakopoulos, G., and Goutis, C. E.

Subjects
EMBEDDED computer systems, ARCHITECTURAL designs, ELECTRONIC systems, INTEGRATED circuits, COMPUTER architecture
Abstract

Current embedded systems are usually designed for data-dominated applications, but they have a tight energy and time budget. Scratch-pad memories are completely software-controlled memories with predictable behaviour and good performance and energy characteristics, thus they tend to become a standard feature in many embedded systems. However, their predictability is not helping if the application accesses its data dynamically, when the addresses of the accessed data depend on the application's input. In such cases, predetermining the scratch-pad content at design-time is not always possible as the compiler cannot predict the runtime input. Moreover, in this case, both data reuse and data placement in the scratch-pad are inefficient because chunks of data already stored cannot be efficiently reused and combined with the runtime accessed data blocks. State-of-the art techniques copy each new data block to the scratch-pad without considering whether portions of them are already in it. Such dynamic temporal locality cannot be predicted or exploited by the compiler. The authors here present a system architecture, strongly connected to the system's scratch-pad and the processor's compiler, which is able to efficiently exploit run-time data reuse in the scratch-pad by being capable of holding valuable information, such as the exact data contents of the scratch-pad at runtime, and using it to do all the necessary operations for placing each new data block in scratch-pad. It is fine tuned for applications with run-time reuse between rectangular data blocks. The application domain of the proposed architecture is multimedia applications with run-time reuse, certain applications with linked lists and multi-threaded applications. It operates in a time and energy-efficient manner when compared with existing scratch-pad architectures without the authors’ scratch-pad accelerator engine, showing its higher normalised performance and lower normalised energy consumption. Experimental results show up to 2.5 times performance increase compared with existing scratch-pad architectures and 5 times compared with cache architectures and energy decrease up to 1.9 and 3.9 times, respectively. [ABSTRACT FROM AUTHOR]

Published
2009
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39. A novel algorithm for low-power image and video coding.

Author

Masselos, K., Merakos, P., Stouraitis, T., and Goutis, C. E.

Subjects
IMAGING systems, VECTOR valued functions
Abstract

Presents information on a proposed algorithm for video coding and decoding and low-power image, which is based on vector quantization. Definition of vector quantization; Information on the estimation of power consumption; In-depth look at the proposed algorithm; Details on the results of experiments which were conducted with the application of the proposed algorithm.

Published
1998
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45. A performance efficient hardware implementation for the encrypted shared storage media standard

Author

Athanasios Kakarountas, Michail, H., Fotopoulou, E., Milidonis, A., Theodoridis, G., Goutis, C. E., and Μιχαήλ, Χάρης

Subjects
Hardware, Security, Cryptography, Engineering and Technology, Storage media, Electrical Engineering - Electronic Engineering - Information Engineering
Abstract

In this paper, the first hardware implementation of P1619 standard for Encrypted Shared Storage Media is proposed. The proposed implementation offers high level of security in accessing shared storage media, achieving at the same time significantly high throughput. Area has kept moderate, turning the implementation suitable for inclusion in hard disks' electronics. The system is based on AES cipher-block. Finally, a comparison to other AES IP cores is offered in order to exhibit the efficiency of the proposed architecture.

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