Search

This article proposes a four-level multilevel converter configuration achieved through the stacking of low voltage basic inverter cells coupled with an cascaded H-bridge (CHB) structure. Three series connected identical capacitors fed from a single common dc source is feeding the CHB converter unit. This results in the formation of two common coupling points (CCPs) along with the dc-link terminals. Ensuring balanced voltages at these CCPs is critical. This is achieved by maintaining zero instantaneous currents drawn or injected from each CCP at any given instant during pulsewidth modulation operation. In addition, this present scheme enables extended linear modulation operation with absence of lower order harmonics, expanding its operational range up to the full base speed of an induction motor drive. This article also presents an capacitor balancing method using a single-step predictive control to achieve balanced capacitor voltages of CHBs effectively. The method entails predicting capacitor voltages for various redundancies, aiming to select the switching vector with minimal deviation from the nominal values using space vector redundancies. This approach enhances the converter's performance by actively regulating the capacitor voltages within each sampling period.

In this article, a modulating waveform generation for carrier-based space vector pulse width modulation (PWM) control for a split-phase induction motor drive is proposed for the first time. The modulating waveform synthesis for the carrier-based dodecagonal space vector PWM (DSV-PWM) is based only on the sampled reference phase amplitude. The present approach for the DSV-PWM generation is based on vector time computation and accessing the output vectors from the look-up table. This article synthesizes a modulating waveform compared to a triangular carrier waveform to generate the DSV-PWM for the two-level conventional split-phase induction motor inverters. Such as conventional hexagonal space vector modulating waveform, here, dodecagonal space vector modulating waveform is generated by adding the zero sequence signals of third, fifth, and seventh order harmonics to the fundamental or modulating signal. A simple approach, like in a hexagonal space vector scheme, is proposed with less mathematical computation, such that it can be easily implemented in the digital platform. The proposed scheme is explained and verified with experimental results.

Z-source inverters (ZSIs) are recent solutions for single-stage power conversion with boosted dc rail voltage. Trans-ZSI, employing a coupled inductor, allows high boost with lower shoot-through duty ratio. Albeit the several advantages, these converters exhibit unsatisfactory performance at low power factor due to discontinuous current conduction modes—a major concern in applications like motor drives at light loads. The objective of this article is to develop an improved Trans-ZSI with multilevel output voltage that performs well irrespective of load power factor. The proposed topology has continuous input current, low input current ripple, and the presence of active switches in the impedance network allows bidirectional current flow. Also, there is output voltage control flexibility by adjusting the coupled inductor turns ratio, shoot-through time, and modulation index. Partial shoot-through states allow nearest three vector switching for obtaining multilevel output voltage and reduced dv/dt. The output stage retains all the advantages of active-neutral-point-clamped (ANPC) inverter. Operating principles, analysis and a ‘simple boost control’ with carrier-based space vector pulse width modulation (CSVPWM) scheme for capacitor balancing are presented. Simulation and hardware results on three-phase, 3 HP, 220 V, 1440 rpm, V/f-controlled induction motor drives are presented to validate the proposed scheme.

In conventional inverters, the linear modulation range is limited to a maximum voltage space vector radius of 0.866 times the dc link voltage ($\text{V}_\text{dc}$), which corresponds to a maximum peak fundamental phase voltage of 0.577 $\text{V}_\text{dc}$. Beyond this, the inverter enters the overmodulation region, where the operation transitions to a six-step mode causing the voltage space vector to trace a hexagonal locus. This results in phase voltage waveforms with significant lower order harmonic content leading to torque ripples in the motor shaft and undesired harmonic losses. Thus, the achievable speed range of the induction motor in the linear modulation range is effectively limited to 90.5% of its full base speed. In contrast, the proposed five-level inverter topology generates a circular voltage space vector locus with a radius of up to 0.955 $\text{V}_\text{dc}$ resulting in a maximum peak fundamental phase voltage of 0.637 $\text{V}_\text{dc}$. Thus, the linear modulation range is extended to full base speed and is independent of the load power factor. The proposed power circuit is based on two standard three-level neutral point clamped inverters and can be realized by two readily available three-level NPC inverter IC packages. Standard space vector pulsewidth modulation techniques can be employed for switching pulse generation.