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Computationally hard combinatorial optimization problems (COPs) are ubiquitous in many applications, including logistical planning, resource allocation, chip design, drug explorations, and more. Due to their critical significance and the inability of conventional hardware in efficiently handling scaled COPs, there is a growing interest in developing computing hardware tailored specifically for COPs, including digital annealers, dynamical Ising machines, and quantum/photonic systems. However, significant hurdles still remain, such as the memory access issue, the system scalability and restricted applicability to certain types of COPs, and VLSI-incompatibility, respectively. Here, a ferroelectric field effect transistor (FeFET) based compute-in-memory (CiM) annealer is proposed. After converting COPs into quadratic unconstrained binary optimization (QUBO) formulations, a hardware-algorithm co-design is conducted, yielding an energy-efficient, versatile, and scalable hardware for COPs. To accelerate the core vector-matrix-vector (VMV) multiplication of QUBO formulations, a FeFET based CiM array is exploited, which can accelerate the intended operation in-situ due to its unique three-terminal structure. In particular, a lossless compression technique is proposed to prune typically sparse QUBO matrix to reduce hardware cost. Furthermore, a multi-epoch simulated annealing (MESA) algorithm is proposed to replace conventional simulated annealing for its faster convergence and better solution quality. The effectiveness of the proposed techniques is validated through the utilization of developed chip prototypes for successfully solving graph coloring problem, indicating great promise of FeFET CiM annealer in solving general COPs., Comment: 39 pages, 12 figures

The mismatch of acoustic impedance at water-air interface can lead a low transmitted sound energy. In this paper, we propose a discrete metasurface for extreme sound transmission based on the impedance matching theory. By employing topology optimization, discrete unit cells with different aspect ratios are designed with unitary sound transmission. The unit cell of continuous metasurface is also obtained for comparison. After analyzing the wide-angle performance of discrete unit cells, samples of both discrete and continuous metasurfaces are fabricated. Sound transmission enhancement of discrete metasurface is clearly measured compared to the bare water-air interface. And the amplitude is relatively larger than that of the continuous sample. Experimental results are in general agreement with numerical ones when viscosity of the sample is considered. Furthermore, the frequency shifts between experiment and simulation are attributed to the random immersion of unit cells for discrete metasurface and the bending of continuous metasurface, respectively. The present work suggests an alternative way for improving the efficiency of water-air acoustic communication., Comment: 18pages, 10figures

For one-dimension Brownian motion in the confined system with the size $L$, the mean-squared displacement(MSD) defined by $\left \langle (x-x_0)^2 \right\rangle$ should be proportional to $t^{\alpha(t)}$. The power $\alpha(t)$ should range from $1$ to $0$ over time, and the MSD turns from $2Dt$ to $c L^2$, here the coefficient $c$ independent of $t$, $D$ being the diffusion coefficient. The paper aims to quantitatively solve the MSD in the intermediate confinement regime. The key to this problem is how to deal with the propagator and the normalization factor of the Fokker-Planck equation(FPE) with the Dirichlet Boundaries. Applying the Euler-Maclaurin approximation(EMA) and integration by parts for the small $t$, we obtain the MSD being $2Dt(1-\frac{2\sqrt{\xi} }{3\pi\sqrt{\pi}})$, with $t_{ch}=\frac{L^2}{4\pi^2D},\xi\equiv \frac{t}{t_{ch}}$, and the power $\alpha(t)$ being $\frac{1-0.18\sqrt{\xi}}{1-0.12\sqrt{\xi}}$. Further, we analysis the MSD and the power for the $d$-dimension system with $\gamma$-dimension confinement. In the case of $\gamma< d$, there exists the sub-diffusive behavior in the intermediate time. The universal description is consistent with the recent experiments and simulations in the micro-nano systems. Finally, we calculate the position variance(PV) meaning $\left\langle (x-\left\langle x \right\rangle)^2 \right\rangle$. Under the initial condition referring to the different probability density function(PDF) being $p_{0}(x)$, MSD and PV should exhibit different dependencies on time, which reflect corresponding diffusion behaviors.As examples, the paper discusses the representative initial PDFs reading $p_{0}(x)=\delta(x-x_0)$, with the midpoint $x_0=\frac{L}{2}$ and the endpoint $x_0=\epsilon$(or $0^+$).The MSD(equal to PV) reads $2Dt(1-\frac{5\pi^3 Dt}{L^2})$,and $\frac{4}{\pi}(2Dt)[1+\frac{2\sqrt{\pi Dt}}{L}]$for the small $t$,respectively., Comment: 18 pages, 4 figurea

We study pure exploration with infinitely many bandit arms generated i.i.d. from an unknown distribution. Our goal is to efficiently select a single high quality arm whose average reward is, with probability $1-\delta$, within $\varepsilon$ of being among the top $\eta$-fraction of arms; this is a natural adaptation of the classical PAC guarantee for infinite action sets. We consider both the fixed confidence and fixed budget settings, aiming respectively for minimal expected and fixed sample complexity. For fixed confidence, we give an algorithm with expected sample complexity $O\left(\frac{\log (1/\eta)\log (1/\delta)}{\eta\varepsilon^2}\right)$. This is optimal except for the $\log (1/\eta)$ factor, and the $\delta$-dependence closes a quadratic gap in the literature. For fixed budget, we show the asymptotically optimal sample complexity as $\delta\to 0$ is $c^{-1}\log(1/\delta)\big(\log\log(1/\delta)\big)^2$ to leading order. Equivalently, the optimal failure probability given exactly $N$ samples decays as $\exp\big(-cN/\log^2 N\big)$, up to a factor $1\pm o_N(1)$ inside the exponent. The constant $c$ depends explicitly on the problem parameters (including the unknown arm distribution) through a certain Fisher information distance. Even the strictly super-linear dependence on $\log(1/\delta)$ was not known and resolves a question of Grossman and Moshkovitz (FOCS 2016, SIAM Journal on Computing 2020).

Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128x128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows around 22.6x/14.1x increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.

CANDECOMP/PARAFAC (CP) decomposition is the mostly used model to formulate the received tensor signal in a multi-domain massive multiple-input multiple-output (MIMO) system, as the receiver generally sums the components from different paths or users. To achieve accurate and low-latency channel estimation, good and fast CP decomposition algorithms are desired. The CP alternating least squares (CPALS) is the workhorse algorithm for calculating the CP decomposition. However, its performance depends on the initializations, and good starting values can lead to more efficient solutions. Existing initialization strategies are decoupled from the CPALS and are not necessarily favorable for solving the CP decomposition. To enhance the algorithm's speed and accuracy, this paper proposes a deep-learning-aided CPALS (DL-CPALS) method that uses a deep neural network (DNN) to generate favorable initializations. The proposed DL-CPALS integrates the DNN and CPALS to a model-based deep learning paradigm, where it trains the DNN to generate an initialization that facilitates fast and accurate CP decomposition. Moreover, benefiting from the CP low-rankness, the proposed method is trained using noisy data and does not require paired clean data. The proposed DL-CPALS is applied to millimeter wave MIMO orthogonal frequency division multiplexing (mmWave MIMO-OFDM) channel estimation. Experimental results demonstrate the significant improvements of the proposed method in terms of both speed and accuracy for CP decomposition and channel estimation.

A probabilistic-bit (p-bit) is the fundamental building block in the circuit network of a stochastic computing, and it could produce a continuous random bit-stream with tunable probability. Utilizing the stochasticity in few-domain ferroelectric material(FE), we propose for the first time, the p-bits based on ferroelectric FET. The stochasticity of the FE p-bits stems from the thermal noise-induced lattice vibration, which renders dipole fluctuations and is tunable by an external electric field. The impact of several key FE parameters on p-bits' stochasticity is evaluated, where the domain properties are revealed to play crucial roles. Furthermore, the integer factorization based on FE p-bits circuit network is performed to verify its functionality, and the accuracy is found to depend on FE p-bits' stochasticity. The proposed FE p-bits possess the advantages of both extremely low hardware coast and the compatibility with CMOS-technology, rendering it a promising candidate for stochastic computing applications., Comment: 23 pages, 7 figures and supplementary materials with 3 notes

Cache serves as a temporary data memory module in many general-purpose processors and domain-specific accelerators. Its density, power, speed, and reliability play a critical role in enhancing the overall system performance and quality of service. Conventional volatile memories, including static random-access memory (SRAM) and embedded dynamic random-access memory (eDRAM) in the complementary metal-oxide-semiconductor technology, have high performance and good reliability. However, the inherent leakage in both SRAM and eDRAM hinders further improvement towards smaller feature sizes and higher energy efficiency. Although the emerging nonvolatile memories can eliminate the leakage efficiently, the penalties of lower speed and degraded reliability are significant. This article reveals a new opportunity towards leakage-free volatile static memory beyond the known paradigms of existing volatile and nonvolatile memories. By engineering a double-well energy landscape with the assistance of a clamping voltage bias, leakage-free and refresh-free state retention of volatile memory is achieved for the first time. This new memory is highlighted by both the ultra-low leakage of nonvolatile memories and the speed, energy, and reliability advantages of volatile memories. A proof-of-concept memory is demonstrated using in-house anti-ferroelectric field-effect transistors (AFeFETs), delivering an extrapolated endurance of about 1012 cycles, a retention time of over 10 years, and no subthreshold channel leakage current. Such a new concept of AFeFET-based memory enables an improved balance between density, power, and reliability beyond all existing memory solutions.

Field Programmable Gate Array (FPGA) is widely used in acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the tradeoff between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. In this paper, we perform technology-circuit-architecture co-design to break this tradeoff with no additional area cost and lower power consumption compared with conventional designs while providing dynamic reconfiguration, which can hide the reconfiguration time behind the execution time. Leveraging the intrinsic transistor structure and non-volatility of ferroelectric FET (FeFET), compact FPGA primitives are proposed and experimentally verified, including 1FeFET look-up table (LUT) cell, 1FeFET routing cell for connection blocks (CBs) and switch boxes (SBs). To support dynamic reconfiguration, two local copies of primitives are placed in parallel, which enables loading of arbitrary configuration without interrupting the active configuration execution. A comprehensive evaluation shows that compared with the SRAM-based FPGA, our dynamic reconfiguration design shows 63.0%/71.1% reduction in LUT/CB area and 82.7%/53.6% reduction in CB/SB power consumption with minimal penalty in the critical path delay (9.6%). We further implement a Super-Sub network model to show the benefit from the context-switching capability of our design. We also evaluate the timing performance of our design over conventional FPGA in various application scenarios. In one scenario that users switch between two preloaded configurations, our design yields significant time saving by 78.7% on average. In the other scenario of implementing multiple configurations with dynamic reconfiguration, our design offers time saving of 20.3% on average., Comment: 54 pages, 15 figures

Three-phase PWM voltage-source rectifier (VSR) systems have been widely used in various energy conversion systems, where current sensors are the key component for state monitoring and system control. The current sensor faults may bring hidden danger or damage to the whole system; therefore, this paper proposed a random forest (RF) and current fault texture feature-based method for current sensor fault diagnosis in three-phase PWM VSR systems. First, the three-phase alternating currents (ACs) of the three-phase PWM VSR are collected to extract the current fault texture features, and no additional hardware sensors are needed to avoid causing additional unstable factors. Then, the current fault texture features are adopted to train the random forest current sensor fault detection and diagnosis (CSFDD) classifier, which is a data-driven CSFDD classifier. Finally, the effectiveness of the proposed method is verified by simulation experiments. The result shows that the current sensor faults can be detected and located successfully and that it can effectively provide fault locations for maintenance personnel to keep the stable operation of the whole system., Comment: Frontiers in Energy Research

In this work, we report a novel design, one-transistor-one-inverter (1T1I), to satisfy high speed and low power on-chip training requirements. By leveraging doped HfO2 with ferroelectricity, a non-volatile inverter is successfully demonstrated, enabling desired continuous weight transition between negative and positive via the programmable threshold voltage (VTH) of ferroelectric field-effect transistors (FeFETs). Compared with commonly used designs with the similar function, 1T1I uniquely achieves pure on-chip-based weight transition at an optimized working current without relying on assistance from off-chip calculation units for signed-weight comparison, facilitating high-speed training at low power consumption. Further improvements in linearity and training speed can be obtained via a two-transistor-one-inverter (2T1I) design. Overall, focusing on energy and time efficiencies, this work provides a valuable design strategy for future FeFET-based computing-in-memory (CiM).

3D NAND enables continuous NAND density and cost scaling beyond conventional 2D NAND. However, its poly-Si channel suffers from low mobility, large device variations, and instability caused by grain boundaries. Here, we overcome these drawbacks by introducing an amorphous indium-gallium-zinc-oxide (a-IGZO) channel, which has the advantages of ultra-low OFF current, back-end-of-line compatibility, higher mobility and better uniformity than poly-Si, and free of grain boundaries due to the amorphous nature. Ultra-scaled floating-gate (FG) transistors with a channel length of 60 nm are reported, achieving the highest ON current of 127 uA/um among all reported a-IGZO-based flash devices for high-density, low-power, and high-performance 3D NAND applications. Furthermore, a non-volatile and area-efficient ternary content-addressable memory (TCAM) with only two a-IGZO FG transistors is experimentally demonstrated. Array-level simulations using experimentally calibrated models show that this design achieves at least 240x array-size scalability and 2.7-fold reduction in search energy than 16T-CMOS, 2T2R, and 2FeFET TCAMs., Comment: 50 pages, 20 figures

We propose a novel algorithm for the computation of canonical polyadic decomposition (CPD) of large-scale tensors. The proposed algorithm generalizes the random projection (RAP) technique, which is often used to compute large-scale decompositions, from one single projection to multiple but coupled random projections (CoRAP). The proposed CoRAP technique yields a set of tensors that together admits a coupled CPD (C-CPD) and a C-CPD algorithm is then used to jointly decompose these tensors. The results of C-CPD are finally fused to obtain factor matrices of the original large-scale data tensor. As more data samples are jointly exploited via C-CPD, the proposed CoRAP based CPD is more accurate than RAP based CPD. Experiments are provided to illustrate the performance of the proposed approach.