10 results on '"Golshan, Shahin"'
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2. MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits
3. SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs
4. Process variation aware system-level load assignment for total energy minimization using stochastic ordering
5. On leakage power optimization in clock tree networks for ASICs and general-purpose processors
6. Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems
7. Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
8. Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.
9. SEU-aware resource binding for modular redundancy based designs on FPGAs.
10. Military Integrated Circuits Screening Report (Summary) ESSEH Parts Committee
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