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We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of $>10^{10}$ read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

Ultrathin ferroelectric materials could potentially enable low-power logic and nonvolatile memories1,2. As ferroelectric materials are made thinner, however, the ferroelectricity is usually suppressed. Size effects in ferroelectrics have been thoroughly investigated in perovskite oxides—the archetypal ferroelectric system3. Perovskites, however, have so far proved unsuitable for thickness scaling and integration with modern semiconductor processes4. Here we report ferroelectricity in ultrathin doped hafnium oxide (HfO2), a fluorite-structure oxide grown by atomic layer deposition on silicon. We demonstrate the persistence of inversion symmetry breaking and spontaneous, switchable polarization down to a thickness of one nanometre. Our results indicate not only the absence of a ferroelectric critical thickness but also enhanced polar distortions as film thickness is reduced, unlike in perovskite ferroelectrics. This approach to enhancing ferroelectricity in ultrathin layers could provide a route towards polarization-driven memories and ferroelectric-based advanced transistors. This work shifts the search for the fundamental limits of ferroelectricity to simpler transition-metal oxide systems—that is, from perovskite-derived complex oxides to fluorite-structure binary oxides—in which ‘reverse’ size effects counterintuitively stabilize polar symmetry in the ultrathin regime. Enhanced switchable ferroelectric polarization is achieved in doped hafnium oxide films grown directly onto silicon using low-temperature atomic layer deposition, even at thicknesses of just one nanometre.

Gokmen and Vlasov proposed that the training of deep neural networks would be dramatically accelerated by the realization of resistive processing units that can store analog weights to minimize data movement during training [1]. Here we measure and evaluate the partial switching of the ferroelectric (FE) PbZrTiO 3 (PZT) and, for the first time, Hf 0 8 Zr 0 2 O 2 , (HZO), formed by atomic layer deposition, for use as a nonvolatile analog memory element. The spontaneous polarization P of a FE can be switched by applying a voltage that exceeds the coercive voltage for switching of the FE. This polarization, when fully switched, can have a value of +P or −P (C/cm2), depending on the polarity of the applied voltage. Ferroelectric memory is typically operated in fully switched +P or −P polarizations, however with short (< 10 μs) pulsed voltages, the FE can be partially switched, i.e. only a fraction of the domains are switched during the pulse duration as shown by Tokumitsu in PZT [2] and indicated in Fig. 1.

Over the past five years, fabrication of metal-insulator-metal (MIM) single electron transistors (SET) featuring atomic layer deposition (ALD) of ultrathin tunnel barrier dielectrics (SiO

Single electron transistors (SET) featuring metal (Ni) electrodes and silicon nitride dielectric barriers prepared by atomic layer deposition are fabricated and tested. Electrical characterization of the devices reveals electrostatic energy parameters consistent with the parameters of the designed tunnel junctions. In addition, an analysis of temperature dependence of conductance confirms the formation of metal-insulator-metal (MIM) junctions with negligible in-series contribution of any surface native metal oxide. However, the fabricated devices exhibit a very high level of electrical noise, far exceeding the commonly observed shot noise. Experimental investigation reveals the random telegraph signal (RTS) nature of the observed excess noise. The RTS noise in electronic devices is commonly associated with charging of external traps that are electrostatically coupled to the SET island. In the devices under study, however, the defects that result in the observed RTS noise are demonstrated to reside within the tunnel junctions. Our results also indicate the critical importance of interface states and surface preparation for achieving good performance of the SETs fabricated using ALD to form the tunnel barrier.

Depletion-mode quaternary barrier In0.13Al0.83 Ga0.04N high-electron-mobility transistors (HEMTs) with regrown ohmic contacts and T-gates on a SiC substrate have been fabricated. Devices with 40-nm-long footprints show a maximum output current density of 1.8 A/mm, an extrinsic dc transconductance of 770 mS/mm, and cutoff frequencies fT/fmax of 230/300 GHz at the same bias, which give a record-high value of √fT ·fmax = 263 GHz among all reported InAl(Ga)N barrier HEMTs. The device speed shows good scalability with gate length despite the onset of short-channel effects due to the lack of a back barrier. An effective electron velocity of 1.36 ×107 cm/s, which is comparable with that in the state-of-the-art deeply scaled AlN/GaN HEMTs, has been extracted from the gate-length dependence of fT for gate lengths from 100 to 40 nm.

We report on the stabilization of the ferroelectric phase in Hf0.8Zr0.2O2 with a tungsten capping layer. Ferroelectricity is obtained in both metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) capacitors with highly-doped Si serving as the bottom electrode in the MIS structure. Ferroelectricity is confirmed from both the electrical polarization-voltage (P-V) measurement and X-Ray Diffraction analysis that shows the presence of an orthorhombic phase. High-resolution Transmission Electron Microscopy and Energy Dispersive X-ray spectroscopy show minimal diffusion of W into the underlying Hf0.8Zr0.2O2 after the crystallization anneal. This is in contrast to significant Ti and N diffusion observed in ferroelectric HfxZr1-xO2 commonly capped with TiN.

Over the past five years, fabrication of metal-insulator-metal (MIM) single electron transistors (SET) featuring atomic layer deposition (ALD) of ultrathin tunnel barrier dielectrics (SiO2, Al2O3) has been reported. However, the performance of fabricated devices was significantly compromised by the presence of native metal oxide and problems associated with the nucleation of ALD dielectrics on metal substrates. To overcome the difficulty of dielectric ALD nucleation on metal substrates, we recently developed a fabrication technique in which the native metal oxide naturally forming in the presence of the ALD oxidant precursor is first used to promote the nucleation of ALD dielectrics, and then is chemically reduced by forming gas anneal (FGA) at temperatures near 400 °C. However, despite the elimination of native oxide, low temperature characterization of the devices fabricated using FGA reveals excess 'switching' noise of a very large magnitude resulting from charged defects within the junctions. It has been previously reported that remote hydrogen plasma (RHP) treatment of SiO2 thin films effectively eradicates fabrication defects. This work reports a comparative study of Ni-based MIM SET treated with FGA and/or RHP. We show that, using a combination of FGA and RHP treatments, it is possible to obtain MIM junctions free of switching noise and without a detectable contribution of native oxide.

Single electron transistors are nanoscale electron devices that require thin, high-quality tunnel barriers to operate and have potential applications in sensing, metrology and beyond-CMOS computing schemes. Given that atomic layer deposition is used to form CMOS gate stacks with low trap densities and excellent thickness control, it is well-suited as a technique to form a variety of tunnel barriers. This work is a review of our recent research on atomic layer deposition and post-fabrication treatments to fabricate metallic single electron transistors with a variety of metals and dielectrics.

This work describes the fabrication of single electron transistors using electron beam lithography and atomic layer deposition to form nanoscale tunnel transparent junctions of alumina (Al2O3) on platinum nanowires using either water or ozone as the oxygen precursor and trimethylaluminum as the aluminum precursor. Using room temperature, low frequency conductance measurements between the source and drain, it was found that devices fabricated using water had higher conductance than devices fabricated with ozone. Subsequent annealing caused both water- and ozone-based devices to increase in conductance by more than 2 orders of magnitude. Furthermore, comparison of devices at low temperatures (∼4 K) showed that annealed devices displayed much closer to the ideal behavior (i.e., constant differential conductance) outside of the Coulomb blockade region and that untreated devices showed nonlinear behavior outside of the Coulomb blockade region (i.e., an increase in differential conductance with source-drain vol...

The authors report the use of plasma-enhanced atomic layer deposition (PEALD) to fabricate single-electron transistors (SETs) featuring ultrathin (≈1 nm) tunnel-transparent SiO2 in Ni-SiO2-Ni tunnel junctions. They show that, as a result of the O2 plasma steps in PEALD of SiO2, the top surface of the underlying Ni electrode is oxidized. Additionally, the bottom surface of the upper Ni layer is also oxidized where it is in contact with the deposited SiO2, most likely as a result of oxygen-containing species on the surface of the SiO2. Due to the presence of these surface parasitic layers of NiO, which exhibit features typical of thermally activated transport, the resistance of Ni-SiO2-Ni tunnel junctions is drastically increased. Moreover, the transport mechanism is changed from quantum tunneling through the dielectric barrier to one consistent with thermally activated resistors in series with tunnel junctions. The reduction of NiO to Ni is therefore required to restore the metal-insulator-metal (MIM) stru...

The fabrication is reported of nanodamascene metallic single electron transistors that take advantage of unique properties of chemical mechanical polishing and atomic layer deposition. Chemical mechanical polishing provides a path for tuning the dimensions of tunnel junctions by adjusting the polish time, surpassing the limits imposed by electron beam lithography and lift-off, while atomic layer deposition provides precise control over the thickness of the tunnel barrier and significantly increases the choices for barrier materials. Single-electron transistor operation of a prototype device was successfully demonstrated at T

In this article, the authors investigate chemical mechanical planarization (CMP) of gold. Our experiments show that the oxidizer concentration, hardness of the adhesion layer, and surfactants added to stabilize the slurry are the main factors determining the outcome of the process. A combination of 30% H2O2 solution and an alumina based slurry in 1:3 volumetric ratio along with added sodium dodecyl sulfate and poly(vinyl pyrrolidone) was successfully used to pattern gold in a CMP Damascene process. After fabricating inlaid gold structures with CMP, the authors observed that pattern density, as opposed to feature size, is the major factor in determining the amount of metal thinning in inlaid features. 10 μm lines at 5% density were thinned down by 40 nm, while 150 μm pads at 75% density were recessed by 20 nm. The authors believe that in this process, metal recess, that is a chemical effect, outweighs dishing, a feature-size dependent factor, in controlling the severity of metal thinning.

Depletion-mode high-electron-mobility transistors (HEMTs) with an 11 nm quaternary In0.13Al0.83Ga0.04N barrier and a 5 nm In0.05Ga0.95N channel on SiC substrates have been fabricated. The as-processed HEMT structure features a channel electron density of 2.08×1013 cm-2 and a mobility of 1140 cm2 V-1 s-1. A device with a 50-nm-long T-shaped gate shows a maximum output current density of 2.0 A/mm, a peak extrinsic DC transconductance of 690 mS/mm, and cut-off frequencies fT/fmax of 260/220 GHz at the same bias, representing a record high √fTfmax of 239 GHz for InGaN channel HEMTs.

The properties of poly(methylglutarimide) (PMGI) when used as an electron beam resist are investigated. The results show that PMGI, when developed with a weak developer, xylenes, shows contrast higher than 12, which is comparable to the contrast achieved in cold developed poly(methylmethacrylate), and approximately twice as high as the recently achieved PMGI contrast using other developers. Using this high contrast polymer, sub 20 nm features with aspect ratios greater than 30:1 can be readily achieved. In addition to the superior positive tone behavior, this polymer behaves as a negative tone resist at higher exposure doses. Negative resist features as small as 20 nm can be fabricated when methyl isobutyl ketone is used to develop negative tone PMGI.