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Thermoelectric generators (TEGs) offer the possibility of extracting electrical power from any heat source, including low-enthalpy heat. The operation of thermoelectric generators is closely related to not only thermal factors but also the electrical load conditions. Consequently, simulations of TEG-based thermoelectric systems require the adequate modeling of both thermal and electric phenomena. In this paper, the developed TEG model is presented and verified through the design of a complete thermoelectric system able to optimize the extraction of electrical power according to the thermal conditions. The system consisted of a TEG, a properly designed low-cost DC/DC converter, and an energy storage element. The DC/DC converter was controlled by a specific algorithm that optimized the electrical power extraction following the maximum power point. The choices adopted for the system design, the implementation of the DC/DC converter, and the algorithm development were verified with experimental measurements.

The increasing energy demand and the ever more pressing need for clean technologies of energy conversion pose one of the most urgent and complicated issues of our age. Thermoelectricity, namely the direct conversion of waste heat into electricity, is a promising technique based on a long-standing physical phenomenon, which still has not fully developed its potential, mainly due to the low efficiency of the process. In order to improve the thermoelectric performance, a huge effort is being made by physicists, materials scientists and engineers, with the primary aims of better understanding the fundamental issues ruling the improvement of the thermoelectric figure of merit, and finally building the most efficient thermoelectric devices. In this Roadmap an overview is given about the most recent experimental and computational results obtained within the Italian research community on the optimization of composition and morphology of some thermoelectric materials, as well as on the design of thermoelectric and hybrid thermoelectric/photovoltaic devices.

Thermoelectric generators made by large arrays of nanowires perpendicular to a silicon substrate, that is, so-called silicon nanowire forests are fabricated on large areas by an inexpensive metal-assisted etching technique. After fabrication, a thermal diffusion process is used for doping the nanowire forest with phosphorous. A suitable experimental technique has been developed for the measurement of the Seebeck coefficient under static conditions, and results are reported for different doping parameters. These results are in good agreement with numerical simulations of the doping process applied to silicon nanowires. These devices, based on doped nanowire forests, offer a possible route for the exploitation of the high power factor of silicon, which, combined with the very low thermal conductivity of nanostructures, will yield a high efficiency of the conversion of thermal to electrical energy.

Thermoelectric generator devices, which convert heat directly into electrical power, have a great potential for energy scavenging and green energy harvesting applications. The exploitation of such a potential requires a proper design of both the electrical circuit that drives the electrical load and the thermal part, in particular when the thermoelectric generator is coupled with the hot and cold heat sources through thermal resistances. We propose a straightforward approach to take into account both thermal and electrical issues, by means of an equivalent electric circuit model that can be solved with widely available simulator programs, such as SPICE. Our approach is shown to be effective for supporting the design and optimization of thermoelectric systems from the point of view of the output power and of the efficiency. In particular, with our model we are able to point out that thermal resistance matching optimizes the thermal fluxes only in first approximation: for a particular case study we find that the optimal module thermal resistance is 20% larger than the contact resistance. We also show that the electrical matching for the maximum output power must be carefully considered for each particular thermoelectric module and load condition.

We report room temperature Hall mobility measurements, low temperaturemagnetoresistance analysis and low-frequency noise characterization of inkjet-printed graphene films on fused quartz and SiO2/Si substrates. We found that thermal annealing in vacuum at 450 C is a necessary step in order to stabilize the Hall voltage across the devices, allowing their electrical characterization. The printed films present a minimum sheet resistance of 23.3 W/sq after annealing, and are n-type doped, with carrier concentrations in the low 1020 cm􀀀3 range. The charge carrier mobility is found to increase with increasing film thickness, reaching a maximum value of 33 cm2 V􀀀1 s􀀀1 for a 480 nm-thick film printed on SiO2/Si. Low-frequency noise characterization shows a 1/f noise behavior and a Hooge parameter in the range of 0.1 – 1. These results represent thefirst in-depth electrical and noise characterization of transport in inkjet-printed graphene films, able to provide physical insights on the mechanisms at play.

Complementary electronics has represented the corner stone of the digital era, and silicon technology has enabled this accomplishment. At the dawn of the flexible and wearable electronics age, the seek for new materials enabling the integration of complementary metal-oxide semiconductor (CMOS) technology on flexible substrates, finds in low-dimensional materials (either 1D or 2D) extraordinary candidates. Here, we show that the main building blocks for digital electronics can be obtained by exploiting 2D materials like molybdenum disulfide, hexagonal boron nitride and 1D materials such as carbon nanotubes through the inkjet-printing technique. In particular, we show that the proposed approach enables the fabrication of logic gates and a basic sequential network on a flexible substrate such as paper, with a performance already comparable with mainstream organic technology.

The field of thermoelectric materials has undergone a revolutionary transformation over the last couple of decades as a result of the ability to nanostructure and synthesize myriads of materials and their alloys. The ZT figure of merit, which quantifies the performance of a thermoelectric material has more than doubled after decades of inactivity, reaching values larger than two, consistently across materials and temperatures. Central to this ZT improvement is the drastic reduction in the material thermal conductivity due to the scattering of phonons on the numerous interfaces, boundaries, dislocations, point defects, phases, etc., which are purposely included. In these new generation of nanostructured materials, phonon scattering centers of different sizes and geometrical configurations (atomic, nano- and macro-scale) are formed, which are able to scatter phonons of mean-free-paths across the spectrum. Beyond thermal conductivity reductions, ideas are beginning to emerge on how to use similar hierarchical nanostructuring to achieve power factor improvements. Ways that relax the adverse interdependence of the electrical conductivity and Seebeck coefficient are targeted, which allows power factor improvements. For this, elegant designs are required, that utilize for instance non-uniformities in the underlying nanostructured geometry, non-uniformities in the dopant distribution, or potential barriers that form at boundaries between materials. A few recent reports, both theoretical and experimental, indicate that extremely high power factor values can be achieved, even for the same geometries that also provide ultra-low thermal conductivities. Despite the experimental complications that can arise in having the required control in nanostructure realization, in this colloquium, we aim to demonstrate, mostly theoretically, that it is a very promising path worth exploring., 72 pages, 13 figures

Silicon nanowires, whose thermal conductivity is strongly reduced with respect to that of the bulk silicon, are very promising for high-efficient thermoelectric conversion. This work focuses on the development of a technique for the fabrication of thermoelectric generators which are based on vertical silicon nanowire forests, achieved through a metal-assisted chemical etch. As heavily doped nanowires are essential in thermoelectric applications, this chemical process has been applied both on lightly and on highly doped (> 1019 cm−3) silicon substrates. A comparison of the results shows that the etch behaves in a completely distinct way when applied to the differently doped substrates. The results of this comparison and a preliminary insight into the diverse behavior occurred are reported. The different initial nucleation of silver, which determines the hole injection, essential to the etching of silicon, seems to be the key point of this different behavior.

Thermoelectric generators, which convert heat directly into electrical power, have great potentialities in the energy harvesting field. The exploitation of these potentialities is limited by the materials currently used, characterized by good thermoelectric properties, but also by several drawbacks. This work presents a silicon-based thermoelectric generator, made of a large collection of heavily p-doped silicon nanostructures. This macroscopic device (area of several mm2) collects together the good thermoelectric features of silicon, in terms of high power factor, and a very reduced thermal conductivity, which resulted in being exceptionally low (1.8 W/(m K), close to the amorphous limit). The generated electrical power density is remarkably high for a Si-based thermoelectric generator, and it is suitable for scavenging applications which can exploit small temperature differences. A full characterization of the device (Seebeck coefficient, thermal conductivity, maximum power output) is reported and discussed.

Thermoelectric Generators (TEGs) are devices for direct conversion of heat into electrical power and bear a great potential for applications in energy scavenging and green energy harvesting. Given a heat source, the conversion efficiency depends on the available temperature difference, and must be maximized for optimal operation of the TEG. In this frame, the choice of materials with high thermoelectric properties should be accompanied by the identification of criteria for an optimal exploitation of the electrical power output. In this work, we briefly review the main properties of TEGs, focusing on the electrical power output and the thermal-to-electrical conversion efficiency. Besides, we discuss principles of operation of TEGs enabling the optimization of the electrical power output, based on the suitable choice of the electrical load. In particular, we comparatively present and discuss the conditions for matching the electrical load&mdash, yielding to maximum power transfer&mdash, and those for maximizing the conversion efficiency. We compare the two conditions applying them to the exploitation of a heat reservoir for energy storage and to the recovery of heat from a heat exchanger. We conclude that the difference between the two conditions is not significant enough to justify the complexity required by the implementation of the maximum efficiency. In addition, we consider the effect of the thermal contact resistance on the electrical power output. Using a simple thermal-electrical model, we demonstrate that the equivalent electrical resistance measured between the terminals of the TEG depends on the thermal exchange. Hence, for maximum power transfer, the electrical load of the TEG should not match its parasitic resistance, but the equivalent electrical resistance in each specific operating conditions, which determine the thermal fluxes. The model can be applied for the development of efficient alternative algorithms for maximum power point tracking.

A large amount of parallel silicon nanowires, placed perpendicularly to a silicon substrate (silicon nanowire forests), have been contacted and assembled in order to fabricate legs of a thermoelectric generator. This paper reports the measurement of the main parameter for thermoelectric applications, which is the thermal conductivity. The reported value, which confirms the strong reduction of the thermal conductivity in nanostructures, is measured on a large amount (>107) of parallel nanowires with a diameter variable in the range 60-120 nm, and takes into account eventual non-uniformities which are unavoidable on surfaces of several mm2. As silicon nanowire forests are very thin, it has been necessary to develop a suitable measurement apparatus. The fabrication of devices based on silicon nanowire forests, the apparatus and the measurement procedure, as well as the the results, are illustrated and discussed.

We demonstrated device architectures implementing suspended InAs nanowires for thermal conductivity measurements. To this aim, we exploited a fabrication protocol involving the use of a sacrificial layer. The relatively large aspect ratio of our nanostructures combined with their low electrical resistance allows to exploit the four-probe 3ω technique to measure the thermal conductivity, inducing electrical self-heating in the nanowire at frequency ω and measuring the voltage drop across the nanostructure at frequency 3ω. In our systems, field effect modulation of the transport properties can be achieved exploiting fabricated side-gate electrodes in combination with the SiO2/Si ++ substrate acting as a back gate. Our device architectures can open new routes to the all-electrical investigation of thermal parameters in III-V semiconductor nanowires, with a potential impact on thermoelectric applications.

The advent of nanotechnology and nanomaterials is opening new perspectives for the achievement of efficient solid-state heat converters. After decades of slow progress, in recent years innovative ideas have been put forward to improve the thermodynamic conversion efficiency and, as a consequence, new thermoelectric nanomaterials have been developed. A key and challenging ingredient for the progress of this research ambit is today the refinement of precise methods for the measurement of the thermoelectric parameters of nanostructures.

SCOUT is the acronym of the new facility developed within the XUVLab laboratory of the Department of Physics and Astronomy of the University of Florence. SCOUT stands for “Small Chamber for Optical UV Tests” and has been designed to perform practical and fast measurements for those experiments requiring an evacuated environment. SCOUT has been thought, designed and manufactured by paying a particular attention to its flexibility and adaptability. The functionality and the capabilities of SCOUT have been recently tested in a measurement campaign to characterize an innovative wire-grid polarizer optimized to work in transmission in the UV band. This paper provides a description of the overall manufactured system and its performance and shows the additional resources available at the XUVLab laboratory in Florence that make SCOUT exploitable by whatever compact (within 1 m) optical experiment that investigates the UV band of the spectrum.

We present an investigation of shot noise in graphene-based Hall sensors, with the purpose of evaluating their detection limit and of developing strategies to improve their characteristics. We perform measurements on two devices, one with a defective contact that could however be used as a gate to control the carrier density in the device and the other with all contacts working. We discuss the results in terms of the dependence of the noise power spectral density on the carrier density and on the DC bias current. Finally, we provide an estimate of the detection limit, pointing out that the approach commonly used in the literature for its evaluation is flawed.

We present a technique for the fabrication of an electrical (and thermal) contact on the top ends of a large number of vertical silicon nanowires, which are fabricated perpendicularly to a silicon wafer (silicon nanowire forest). The technique is based on electrochemical deposition of copper and has been developed on silicon nanowire forests, fabricated by metal assisted chemical etching. We demonstrate that copper grows selectively only on the top end of the silicon nanowires, forming a layer onto the top of the forest. The presence of a predeposited metal seed is fundamental for the selective growth, meanwhile the process is very strong with respect to other parameters, such as concentration of the electrolytic solution and current density, used during the metal deposition. Typical I–V characteristics of top-to-bottom conduction through silicon nanowire forests with different n-doping are shown and discussed.

Polycrystalline silicon–germanium (poly-SiGe) is a promising structural material for the post-processing of micro electro-mechanical systems (MEMS) on top of complementary metal-oxide-semiconductor (CMOS) substrates. Combining MEMS and CMOS allows for the development of high-performance devices. We present for the first time selective protein immobilization on top of poly-SiGe surfaces, an enabling technique for the development of novel poly-SiGe based MEMS biosensors. Active regions made of 3-aminopropyl-triethoxysilane (APTES) were defined using silane deposition onto photoresist patterns followed by lift-off in organic solvents. Subsequently, proteins were covalently bound on the created APTES patterns. Fluorescein-labeled human serum albumin (HSA) was used to verify the immobilization procedure while the binding capability of the protein layer was tested by an antigen-labeled antibody pair. Inspection by fluorescence microscopy showed protein immobilization inside the desired bioactive areas and low non-specific adsorption outside the APTES pattern. Furthermore, the quality of the silane patches was investigated by treatment with 30 nm-diameter gold nanoparticles and scanning electron microscope observation. The developed technique is therefore a promising first step towards the realization of poly-SiGe based biosensors.

The process for the fabrication of devices based on a single silicon nanowire with a triangular section is presented and discussed. The top down fabrication process exploits the properties of silicon anisotropic etching for the realization of very regular trapezoidal structures, that can be uniformly reduced in controlled way by means of lateral oxidation. This allows the reproducible realization of nanowires smaller than 20nm, and with a length of several micrometers, starting from relatively big structures that, even if electron beam lithography has been used in the present work, could be realized also by other (as optical) lithographic techniques. Nanowires are already placed between silicon contacts for electrical transport characterization. The process, compatible with the actual MOS technology, is suitable for a massive, large-scale production of silicon nanowire based devices and it allows a flexible platform for multigate and more complex structures and devices. The nanowire triangular section is a step toward the integration of three-dimensional devices. Electrical characteristics of silicon nanowire FETs, both p- and n-doped, will be reported and discussed.

In this paper, the most recent achievements in the field of device fabrication, based on nanostructured silicon, will be reviewed. Top-down techniques for silicon nanowire production based on lithography, oxidation and highly anisotropic etching (wet, plasma and metal assisted) will be discussed, illustrating both advantages and drawbacks. In particular, fabrication processes for a massive production of silicon nanowires, organized and interconnected in devices with macroscopic dimensions, will be shown and discussed. These macroscopic devices offer the possibility of exploiting the nanoscale thermoelectric properties of silicon in practical applications. In particular, the reduced thermal conductivity of silicon nanowires, with respect to bulk silicon, makes possible to obtain high efficiencies in the direct conversion of heat into electrical power, with intriguing applications in the field of green energy harvesting. The main experiments elucidating the electrical and thermal properties of silicon nanowire devices will be shown and discussed, and compared with the recent theoretical works developed on the subject.

In this work, we propose a fabrication process for a single-electron transistor on silicon. The process is developed on silicon on insulator wafer and it is based on electron beam lithography and KOH anisotropic etching. A structure composed by a small silicon isle connected to the leads by channels with triangular cross-section is obtained. Channel dimensions have been reduced by oxidation and the substrate has been used as backgate. Preliminary I-V characteristics show phenomena of charge/discharge at room temperature.

A process for fabricating a device based on tunneling through a very thin vertical silicon membrane is presented. The process has been developed on a ?1 1 0? oriented silicon wafer using high resolution e-beam lithography and KOH anisotropic etching to define the structure. A single evaporation step allows the fabrication of both the source-drain contacts and a control gate self aligned to the top of the silicon membrane. A vertical silicon membrane with a thickness of 15 nm has been obtained.

We report on the transport properties of a system composed of single-wall carbon nanotubes (SWNTs) noncovalently linked to a new electrically conducting dendrimer poly(amidoamine) modified with a substituted naphthalenediimide (PAMAMC). SEM images show how the adsorption of the conducting dendrimer on SWNTs leads to the unroping of the bundles. The adsorption of PAMAMC molecules on SWNTs has been also investigated by electrical transport measurements. The electrical conductance of SWNTs drastically increases upon adsorption of conducting dendrimer. UV–Vis spectroscopy indicates that there was a modification in the electronic structure of the dendrimer as consequence of nanotube introduction while the appearance of new bands on the Raman spectra may suggest that metallic nanotubes are selectively functionalized.

In this paper we report a new approach to fabricate gated silicon microtip arrays for field emission applications using a single mask process. The key role in the fabrication process is played by the photoelectrochemical etching of silicon in HF-based electrolytes. This technique is here exploited to produce highly uniform silicon microtip arrays. The fabrication process is detailed and the dependence of the tip geometry on the electrochemical etching parameters is discussed.

Cadmium arachidate Langmuir–Blodgett multilayers were used to grow semiconducting cadmium sulphide (CdS) nanoclusters on the surface of self-assembled carbon nanotubes (CNTs). The formation of CdS in the multilayers was determined by TEM, infrared and UV–Vis spectroscopy. We suggest that the conductivity type of CdS nanoparticles modified nanotubes can be changed to n-type. Thermally stimulated current measurements confirm that the photoinduced oxygen adsorption process in CdS/CNTs sample is an important mechanism via the dominant role of the surface in the electrical properties. These issues have important technological implications for the practical use of these nanocomposite systems in novel nanostructured devices.

Silicon is a material with very good thermoelectric properties, with regard to Seebeck coefficient and electrical conductivity. Low thermal conductivities, and hence high thermal to electrical conversion efficiencies, can be achieved in nanostructures, which are smaller than the phonon mean free path but large enough to preserve the electrical conductivity. We demonstrate that it is possible to fabricate a leg of a thermoelectric generator based on large collections of long nanowires, placed perpendicularly to the two faces of a silicon wafer. The process exploits the metal assisted etching technique which is simple, low cost, and can be easily applied to large surfaces. Copper can be deposited by electrodeposition on both faces, so that contacts can be provided, on top of the nanowires. Thermal conductivity of silicon nanowire forests with more than 107 nanowires mm-2 have been measured; the result is comparable with that achieved by several groups on devices based on few nanowires. On the basis of the measured parameters, numerical calculations of the efficiency of silicon-based thermoelectric generators are reported, and the potentialities of these devices for thermal to electrical energy conversion are shown. Criteria to improve the conversion efficiency are suggested and described.

Conventional techniques for thermal conductivity measurements can lead to unreliable results when applied to nanostructures because heaters and temperature sensors needed for the measurement cannot have a negligible size and therefore perturb the result. In this paper, we focus on the 3ω technique, applied to the evaluation of the thermal conductivity of suspended silicon nanoribbons. We introduce a numerical approach based on the finite element solution of the electrical and thermal transport equations and compare its results with those of conventional methods. We show that with our approach we achieve an excellent fit of the experimental data, in particular, for nanostructured materials.

The completed detailed design and initial phases of construction of an optoelectronic crossbar demonstrator are presented. The experimental system uses hybrid very large scale integrated optoelectronics technology whereby InGaAs-based detectors and modulators are flip-chip bonded onto silicon integrated circuits. The system aims to demonstrate a 1-Tb/s aggregate data input/output to a single chip by means of free-space optics.

A smart flow sensor capable of measuring two distinct gas flows with two different linearity ranges is proposed. The device is based on a chip, designed with a commercial CMOS process, which includes different sensing structures and a read-out interface. The chip is fabricated applying a post-processing technique based on a silicon anisotropic etching in a TMAH solution. A simple and low cost packaging technique is used to convey two distinct gas flows to two selected sensing structures by means of channels of different cross sections. Three methods for sealing the interface between the chip and the gas conveyor are proposed and discussed.

RuO2 thin films have been produced on silicon-based substrates by in situ pulsed laser deposition for the first time. The electrical properties, the surface characteristics, the crystalline structure, and the film-substrate interface of deposited samples have been investigated by 4-probe resistance versus temperature technique, scanning electron microscopy, x-ray photoelectron spectroscopy, x-ray diffraction, and transmission electron microscopy, respectively. The films show good electrical properties. The RuO2-substrate interface is very thin (≈3 nm), since it is not degraded by any annealing process. These two characteristics render our films suitable to be used as electrodes in PZT-based capacitors.

The transport in free‐standing porous silicon layers has been investigated by applying a current step to samples with a four contact geometry and by measuring the voltage time behavior across the voltage contacts. The voltage response showed a transient waveform typical of a network with two time constants and a continuous regime for very long times. The values of the time constants τ1 and τ2 differ noticeably, τ1 and τ2 being in the range 0.1–10 milliseconds and 10–150 milliseconds, respectively. The dependence of the time constants on the current step amplitude and on the temperature has been also investigated. Both τ1 and τ2 showed a temperature activated behavior, which can be related to the resistance behavior vs absolute temperature.

We report the observation of visible and stable room temperature photoluminescence (PL) from thin composite Si SiO 2 films deposited onto various substrates (Si, SiO2, Al and C) by means of an ion-beam sputtering system. Transmission electron microscopy (TEM) observations of the films deposited on carbon substrates reveal the presence of filamentary structures, with nanometric dimensions, of crystalline silicon embedded in an amorphous matrix. While changes of film composition do not influence the main features of the PL, we found that the PL shape and intensity is strongly dependent on the nature of the substrate. The necessary combination of Si and SiO2 for producing the light-emitting material and the TEM results suggest that quantum confinement of carriers in the silicon nanocrystals is a possible origin of the observed PL.

Traditional [Median time to Failure (MTF)] and non traditional (Noise measurements) techniques have been used to characterize four types of Al based samples. Relatively weak stress conditions, which cause negligible modifications to the sample structure, have been used for noise measurements, whereas more accelerated stress conditions have been used for lifetime tests. Quite different results have been obtained by the two types of characterization. In fact, the experimental data showed that the noise measurements are useful to evaluate the activation energy at relatively weak stress conditions, but cannot be used to foresee the behavior of the samples at strongly accelerated stress conditions. This is particularly true in the case of samples containing copper which probably undergo significant microstructural modifications as the temperature goes up. Moreover, the results of a simple computer simulation which show the dramatic effect on the Time to Failure of the spreading of the values of the thermal resistance of the samples are reported.

We measured the macroscopic Seebeck coefficient of silicon nanowires (SiNWs), organized "in a highly interconnected networks on large areas (order of mm(2)). The fabricated networks are very reliable with respect to random nanowire failure and are electrically and thermally equivalent to many SiNWs placed in parallel between the electrical contacts. The equivalent SiNWs have a macroscopic length of the order of millimeters and are very narrow (width smaller than 100 nm) so that they can be used to exploit thermoelectric properties at nanoscale for macroscopic electrical power generation and/or cooling. The measurement of the Seebeck coefficient S, facilitated by the macroscopic dimensions of the network, gives an insight into two questions, nanowire effective doping and carrier mobility, which are widely discussed in the literature. We found that the measured value of S is compatible with an effective doping that is higher than that of the original wafer. This higher doping is consistent with the value estimated from the measured electrical conductivity of the SiNWs with the assumption that the electron mobility inside the nanowire is equal to that of bulk silicon.

The low thermal conductivity of silicon nanowires and nanostructures opens interesting opportunities for energy harvesting through the direct, high-efficiency, conversion of waste heat into electrical power. We present solutions for the fabrication and interconnection of a high number of suspended silicon nanostructures, within CMOS compatible top-down processes. Mechanical stability and thermoelectric properties of these devices will be analysed by means of finite element simulations, and opportunities for practical applications will be discussed. It will be shown that, despite the reduced dimensions needed for a strong suppression of thermal conductivity, a considerable amount of electrical power can be delivered to the load as a result of the presence of many interconnected devices on the same chip.

In this work, we report experimental evidence of surface stress effects on the mechanical properties of silicon nanostructures. As-fabricated, top-down silicon nanowires (SiNWs) are bent up without any applied force. This self-buckling is related to the surface relaxation that reaches an equilibrium with bulk deformation due to the material elasticity. We measure the SiNW self-deformation by atomic force microscopy (AFM), and we apply a simple physical model in order to give an estimation of the surface stress. If the equilibrium is altered by a nanoforce, applied by an AFM tip, nanowires find a new equilibrium condition bending down (mechanical bistability). In this work, for the first time, we report a clear and quantitative relationship between the SiNWs' apparent Young's modulus, measured by force-deflection spectroscopy, and the estimated value of surface stress, obtained by self-buckling measurements taking into account the Young's modulus of bulk silicon. This is an experimental confirmation that the surface stress is fundamental in determining mechanical properties of SiNWs, and that the elastic behavior of nanostructures strongly depends on their surfaces.

Within the Section of Astronomy of the Department of Physics and Astronomy of the University of Firenze (Italy), the XUVLab laboratory is active since 1998 dedicated to technological development, mainly UV oriented. The technological research is focused both on electronics and optics. Our last approach is dedicated to the development of innovative wiregrid polarizers optimized to work in transmission at 121.6 nm. The manufacturing of such optical devices requires advanced technological expertise and suitable experimental structures. First, nanotechnology capability is necessary, in order to build several tiny parallel conductive lines separated by tens of nanometers on wide areas to be macroscopically exploitable in an optical laboratory. Moreover, the characterization of such an advanced optical device has to be performed in vacuum, being air absorptive at 121.6 nm. A dedicated small vacuum chamber, SCOUT (Small Chamber for Optical UV Tests) was developed within our laboratory in order to perform practical and fast measurements. SCOUT hosts an optical bench and is equipped with several opening flanges, in order to be as flexible as possible. The flexibility that has been reached with SCOUT allows us to use the chamber beyond the goals it was thought for. It is exploitable by whatever compact (within 1 m) optical experiment that investigates the UV band of the spectrum.

Direct patterning of silicon dioxide by means of electron beam stimulated etching is shown, and a full characterization of exposure dose is presented. For its high dose, this technique is unsuitable for large areas but can be usefully employed like a precision scalpel for removing silicon dioxide by well-localized points. In this work, this technique is applied to the definition of windows through the oxide surrounding top down fabricated n-doped silicon nanowires. These windows will be employed for a selective doping of the nanowire by boron diffusion. In this way, pn junctions can be fabricated in well-localized points in the longitudinal direction of the nanowire, and an electrical contact to the different junctions can be provided. Electrical I-V characteristics of a nanowire with pn longitudinal junctions are reported and discussed.

A top down process for the reliable fabrication of very complex, large area (order of millimeter square), nets of well organized and connected silicon nanowires (SiNWs) is shown and discussed. It will be shown that these nets are equivalent to the parallel of many very narrow, millimeter long, silicon nanowires, that can be employed either for the fabrication of high efficiency thermoelectric generators or for nanosensing devices. The high reliability with respect to nanowire failure and the high tolerance with respect to silicon nanowire width dispersion are demonstrated by means of numerical simulations. Electrical measurements are reported and compared with numerical simulations, in order to confirm both the equivalence of the net to the parallel of millimeters long SiNWs and its high tolerance with respect to nanowire failure.

A single-chip smart flow sensor based on a thermal principle is presented. The device is fabricated through a commercial complementary metal-oxide- semiconductor (CMOS) process combined with a postprocessing procedure. A configurable electronic interface performing signal reading and nonideality compensation is integrated with the sensing structures on the same chip. The interface implements recently proposed approaches to offset and pressure effect compensation. Detailed experimental results are presented demonstrating correct operation of the proposed microsystem.

We report our work on the characterization by electrically detected magnetic resonance (EDMR) measurements of silicon nanowires (SiNWs) produced by different top-down processes. SiNWs were fabricated starting from SOI wafers using standard e-beam lithography and anisotropic wet etching or by metal-assisted chemical etching. Further oxidation was used to reduce the wire cross section. Different EDMR implementations were used to address the electronic wave function of donors (P) and to characterize point defects at the SiNWs/SiO2 interface. The EDMR spectra of as produced SiNWs with high donor concentration ([P]= 10(18) cm(-3)) show a single line related to delocalized electrons. SiNWs produced on substrates with lower donor concentration ([P] < 10(16) cm(-3)) reveal the doublet related to substitutional P in Si, as well as lines related to interfacial defects such as Pb-0, Pb, E', and E'-like. The EDMR spectra of samples produced by metal-assisted chemical etching exposed to post production oxidation reveal a disordered and defective interface and the disappearance of the P related signal. Forming gas annealing, on the other hand, reduces the contribution of interfacial defects and allows a better resolution of the P related doublet

A compact anemometer based on integrated flow sensors is presented. The device exploits a recently proposed approach, by which the pressure induced on the lateral surface of a cylinder exposed to the wind is converted into two air flow rates exhibiting sinusoidal dependence on the wind direction. A significant size reduction and assemblage simplification were achieved by sensing the two flows by means of a double channel flow meter, integrated on a single silicon chip. The results of measurements, performed over a wind velocity range 0.4-7.9 m/s, demonstrated the effectiveness of the proposed anemometer.

Four contact current voltage characteristics of high aspect ratio, moderately doped silicon nanowires will be presented and discussed. A nonlinear behavior of the current as a function of the voltage drop has been detected, at room temperature, in small silicon nanowires: the current increases quadratically with respect to the voltage drop increasing. The dependency of this nonlinear behavior with temperature is reported. In this work it will be shown that a possible explanation of this effect can be given taking in account the silicon nanowire surface roughness, that drives the carrier backscattering. This hypothesis is supported by Monte Carlo simulations based on a simple model. The simulation results are in qualitative agreement with the experimental data.