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This article presents a compact analog-to-digital converter (ADC)/digital-to-analog converter (DAC) digital signal processing (DSP)-based long reach (LR) transceiver in 7-nm FinFET technology that operates seamlessly from 3.5—56 Gb/s in pulse-amplitude modulation (PAM-4) [from 1.25 to 28 Gb/s in non-return to zero (NRZ) mode] and consumes only 243 mW at 56 Gb/s. The receiver (RX) front end consists of a two-stage continuous-time linear equalizer (CTLE), a 40-way time-interleaved (TI) successive approximation register (SAR)-ADC, a DSP equalizer containing a 17-tap feed-forward equalizer (FFE) working concurrently with a one-tap speculative decision feedback equalizer (DFE) and a reflection canceling FFE, which implements four individually roaming taps. Clock recovery is achieved on a dedicated low latency path consisting of a five-tap FFE, slicer, time error detector (TED), and loop filter driving a dedicated LC —digital-controlled oscillator (DCO). The transmit section consists of a variety of pattern generators, a five-tap finite impulse response (FIR) section, and a terminated DAC as an analog transmitter. When working on a 42.5-dB-LR channel at 56 Gb/s PAM-4, the transceiver consumes 243 mW from the 0.9-V (analog) and 0.75-V (digital) supplies, corresponding to an efficiency of 4.3 pJ/b.

The enormous availability of data on the internet and the increased computational power available in the cloud require a constant increase in the bandwidth needed to transport data across the network. In order to mitigate the cost of infrastructure, the industry has proposed standards for 56Gb/s PAM-4 interfaces that can support legacy channels in conjunction with forward error correction (FEC) techniques. The reduced signal to noise ratio (SNR) available with PAM-4 modulation vs. NRZ requires sophisticated signal processing, making DSP-based solutions very attractive in terms of performance but, so far, at the expense of extra power vs. classical analog solutions. This paper demonstrates that this trade-off can be broken and presents a compact ADC/DAC DSP-based long-reach transceiver in 7nm FinFET technology that operates seamlessly from 3.5-to60Gb/s in PAM-4 (from 1-to-30Gb/s in NRZ mode) and consumes less than 250mW at 56Gb/s. The presented IP extends the deployment of DSP-based transceivers from repeater/re-timer applications to big ASICs with a very large number of ports.

This paper presents a class G amplifier based on a low distortion switching principle technique called switching currents injection. The switching circuit enables a very smooth handover between the voltage supply rails obtaining both high efficiency and low distortion. An approach for the evaluation of the switching distortion in a class G amplifier (and the ability of the loop to reject it) is proposed and the results obtained are used to optimize the overall distortion after compression by the feedback loop. The integrated 65 nm CMOS class G headphone driver based on the above concept operates from ±1.4 V and ±0.35 V supplies. At low power level it uses almost exclusively the low voltage supply reducing the dissipation to 1.63 mW @ Pout = 0.5 mW into 32 Ω. At higher power level, where both supplies are used, the smooth transition between the rails allows a THD + N better than -80 dB for Pout ≤ 16 mW into 32 Ω. The SNR is 101 dB, quiescent power is 0.41 m W and active die area is 0.14 mm2.

A fully-integrated PRML read/write IC with digital adaptive FIR operating up to 450 Mbit/s is presented, The chip implements an EPR4 Viterbi detector as well as a digital servo. The device is integrated in a 0.35 /spl mu/m BiCMOS technology, has a die size of 11.44 mm/sup 2/ (step and repeat) and dissipates 1.3 W (in read mode) at 450 Mbit/s.

A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 /spl mu/m BiCMOS technology with a die size of 13 mm/sup 2/ (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s.