201 results on '"Gi-Joon Nam"'
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2. Cloud-Bursting and Autoscaling for Python-Native Scientific Workflows Using Ray.
3. A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions.
4. SyncTREE: Fast Timing Analysis for Integrated Circuit Design through a Physics-informed Tree-based Graph Neural Network.
5. Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks.
6. FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer.
7. Fault-Criticality Assessment for AI Accelerators using Graph Convolutional Networks.
8. DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.
9. BISTLock: Efficient IP Piracy Protection using BIST.
10. Routing-Free Crosstalk Prediction.
11. Self-Aligned Double-Patterning Aware Legalization.
12. Latch Clustering for Timing-Power Co-Optimization.
13. Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing.
14. Interconnect Optimization Considering Multiple Critical Paths.
15. On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques.
16. End-to-End Industrial Study of Retiming.
17. Integrated Latch Placement and Cloning for Timing Optimization.
18. Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
19. OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing.
20. Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks
21. ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator.
22. Toward Metrics of Design Automation Research Impact.
23. Smart grid load balancing techniques via simultaneous switch/tie-line/wire configurations.
24. Applying VLSI EDA to energy distribution system design.
25. DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing.
26. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
27. Wire delay variability in nanoscale technology and its impact on physical design.
28. Placement: Hot or Not?
29. Guiding a physical design closure system to produce easier-to-route designs with more predictable timing.
30. DATC RDF: Robust design flow database: Invited paper.
31. The ISPD-2011 routability-driven placement contest and benchmark suite.
32. Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power.
33. Floorplanning challenges in early chip planning.
34. DATC RDF: an academic flow from logic synthesis to detailed routing.
35. ITOP: integrating timing optimization within placement.
36. What makes a design difficult to route.
37. Design-hierarchy aware mixed-size placement for routability optimization.
38. New placement prediction and mitigation techniques for local routing congestion.
39. Detecting tangled logic structures in VLSI netlists.
40. Development of 3D tomosynthesis technique for nondestructive technology application using vertically aligned carbon nanotube-based high-resolution cold cathode electron beam
41. CRISP: Congestion reduction by iterated spreading during placement.
42. Guest Editors' Introduction: Hardware Accelerators for Data Centers.
43. The ISPD global routing benchmark suite.
44. RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.
45. Performance modeling for early analysis of multi-core systems.
46. Hippocrates: First-Do-No-Harm Detailed Placement.
47. The nuts and bolts of physical synthesis.
48. RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
49. An accurate sparse matrix based framework for statistical static timing analysis.
50. A semi-persistent clustering technique for VLSI circuit placement.
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