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Vertical three-terminal electrochemical random access memory (ECRAM) is developed to demonstrate the feasibility of high-density integration and mass production. Improved retention was obtained by investigation of role of the electrolyte layer.

Lately, there has been a rapid increase in the use of software-based deep learning neural networks (S-DNN) for the analysis of unstructured data consumption. For implementation of the S-DNN, synapse-device-based hardware DNN (H-DNN) has been proposed as an alternative to typical Von-Neumann structural computing systems. In the H-DNN, various numerical values such as the synaptic weight, activation function, and etc., have to be realized through electrical device or circuit. Among them, the synaptic weight that should have both positive and negative numerical values needs to be implemented in a simpler way. Because the synaptic weight has been expressed by conductance value of the synapse device, it always has a positive value. Therefore, typically, a pair of synapse devices is required to realize the negative weight values, which leads to additional hardware resources such as more devices, higher power consumption, larger area, and increased circuit complexity. Herein, we propose an alternative simpler method to realize the negative weight (named weight shifter) and its hardware implementation. To demonstrate the weight shifter, we investigated its theoretical, numerical, and circuit-related aspects, following which the H-DNN circuit was successfully implemented on a printed circuit board.

Stasis weight ( $$\hbox {G}_s$$ ) that is an independent weight on applied input pulse amplitude was demonstrated for multinary data processing in a synaptic device-based neuromorphic system. Because multinary data is implemented as various input pulse amplitudes, the $$\hbox {G}_s$$ is necessary for high inference accuracy. Typically, synaptic devices exhibit nonlinear current–voltage characteristics (nonlinear device) and have different weight values depending on the applied input pulse amplitudes ( $$\hbox {G}_{{\mathrm{ns}}}$$ ). Therefore, to achieve high inference accuracy, we proposed pulse modulation circuits that can transform the pulse amplitude into pulse width or number. As a result, the $$\hbox {G}_s$$ was obtained from the nonlinear device possessing the $$\hbox {G}_{{\mathrm{ns}}}$$ , and the inference accuracy of the simulated MNIST data set was obviously improved from 29.34% to 97.6%.

Synapse devices are essential for the hardware implementation of neuromorphic computing systems. However, it is difficult to realize ideal synapse devices because of issues such as nonlinear conductance change (linearity) and a small number of conductance states (dynamic range). In this study, the correlation between the linearity and dynamic range was investigated. Consequently, we found a trade-off relationship between the linearity and dynamic range and proposed a novel training method to overcome this trade-off.

To realize a hologram that is an effective method for implementing three-dimensional display, a novel spatial light modulator (SLM) that can generate the hologram by light interference and diffraction was developed based on transmittance changes. For a high-resolution hologram, pixel size of the SLM needs to be scaled down to visible light wavelength (380∼780 nm). However, conventional liquid crystal or micro-mirror-based SLM has a limitation in scaling down; few micrometers sized unit parts are required based on its operation mechanism. Herein, an ion intercalation-based SLM utilizing nano-scale ions as the unit part was investigated. Consequently, basic operations of the SLM (light interference and diffraction) are achieved based on the gradual transmittance changes, which demonstrates the feasibility of ion intercalation-based SLM.

In this research, we propose a method that can significantly improve the linearity of current–voltage characteristics (L–IV) of synapse devices. Considering that analog input data are dependent on the L–IV, synapse devices having non-linear current–voltage characteristics can result in drastic conductance variations during inference operations. It means that the L–IV is one of the key parameters in the synapse device. To improve the L–IV, a triode region of a metal oxide semiconductor field effect transistor (MOSFET) was utilized with a Li-ion-based memristor as a gate voltage divider, which results in gradual channel conductance changes (analog synaptic weights). The channel conductance of the MOSFET can be selectively controlled based on Li-ion intercalation and de-intercalation. A notably improved L–IV and analog synaptic weights were achieved, which enhanced the MNIST data set recognition accuracy from 35.8% to 92.03%.