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19 results on '"Gatefait, M."'

3. AGILE integration into APC for high mix logic fab

Author

Gatefait, M., additional, Lam, A., additional, Le Gratiet, B., additional, Mikolajczak, M., additional, Morin, V., additional, Chojnowski, N., additional, Kocsis, Z., additional, Smith, I., additional, Decaunes, J., additional, Ostrovsky, A., additional, and Monget, C., additional

Published
2015
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4. Silicon Gate etching Using Amorphous Carbon Hard Mask

Author

Lazzarino, F., Pelissier, B., Chevolleau, T., Cunge, G., Vallier, L., Joubert, O., Gouraud, P., Bernard, H., Broekaart, M., Chaton, C., Chapon, J.D, Warrick, S., Gatefait, M., Laboratoire des technologies de la microélectronique (LTM), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS), Clot, Marielle, and Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS)

Subjects
ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2005

5. How holistic process control translates into high mix logic fab APC?

Author

Le-Gratiet, B., additional, Gatefait, M., additional, Ducotè, J., additional, Decaunes, J., additional, Lam, A., additional, Beraud, B., additional, Mikolajczak, M., additional, Pelletier, A., additional, Orlando, B., additional, Sundermann, F., additional, Ostrovsky, A., additional, and Lapeyre, C., additional

Published
2014
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6. Challenges in CMOS‐based images

Author

Roy, Francois, primary, Tournier, A., additional, Wehbe‐Alause, H., additional, Blanchet, F., additional, Boulenc, P., additional, Leverd, F., additional, Favennec, L., additional, Perrot, C., additional, Pinzelli, L., additional, Gatefait, M., additional, Cherault, N., additional, Jeanjean, D., additional, Carrere, J. P., additional, Augier, C., additional, Ricq, S., additional, Herault, D., additional, and Hulot, S., additional

Published
2013
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10. Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology

Author

Fenouillet-Beranger, C., primary, Perreau, P., additional, Pham-Nguyen, L., additional, Denorme, S., additional, Andrieu, F., additional, Tosti, L., additional, Brevard, L., additional, Weber, O., additional, Barnola, S., additional, Salvetat, T., additional, Garros, X., additional, Casse, M., additional, Cassé, M., additional, Leroux, C., additional, Noel, J.P, additional, Thomas, O., additional, Le-Gratiet, B., additional, Baron, F., additional, Gatefait, M., additional, Campidelli, Y., additional, Abbate, F., additional, Perrot, C., additional, de-Buttet, C., additional, Beneyton, R., additional, Pinzelli, L., additional, Leverd, F., additional, Gouraud, P., additional, Gros-Jean, M., additional, Bajolet, A., additional, Mezzomo, C., additional, Leyris, C., additional, Haendler, S., additional, Noblet, D., additional, Pantel, R., additional, Margain, A., additional, Borowiak, C., additional, Josse, E., additional, Planes, N., additional, Delprat, D., additional, Boedt, F., additional, Bourdelle, K., additional, Nguyen, B.Y., additional, Boeuf, F., additional, Faynot, O., additional, and Skotnicki, T., additional

Published
2009
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15. Challenges in CMOS-based images.

Author

Roy, Francois, Tournier, A., Wehbe-Alause, H., Blanchet, F., Boulenc, P., Leverd, F., Favennec, L., Perrot, C., Pinzelli, L., Gatefait, M., Cherault, N., Jeanjean, D., Carrere, J. P., Augier, C., Ricq, S., Herault, D., and Hulot, S.

Subjects
COMPLEMENTARY metal oxide semiconductors, SIGNAL-to-noise ratio, CROSSTALK, PIXELS, PHOTODIODES
Abstract

High resolution CMOS image sensor demand is driven by consumer applications like mobile phone or digital still camera. To maintain the image quality, we have to save the signal to noise ratio (SNR) despite the number of photons reduction gathered by the pixel. In this paper, we present how back-side illumination technology could help to recover signal and how to optimize the process and device in order to reduce the noise. A quantum efficiency larger than 70% is targeted to justify efforts done on BSI process development. We also have to pay attention to pixel to pixel crosstalk coming from free carrier diffusion. To overcome this parasitic phenomenon, deep trench isolation (DTI) should be considered in order to significantly reduce crosstalk between two neighboring pixels. The second main noise contributor related to BSI process is the dark current signal. Dark current less than 1 aA per pixel at room temperature is mandatory to save the image quality at low light level. Therefore, all the Si-SiO2 interfaces at the pixel side walls have to be processed without any process damage to reduce as much as possible the surface defects. On top of that, side wall implantation and side wall dielectric fabrication have been optimized to reduce this noise source. The pixel layout has to be fully optimized also to collect and store charges properly. With respect to the 3D pixel shape, a new fully depleted pinned photodiode with vertical charge storage and no lag has been developed. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

Published
2014
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