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Data-parallel applications, such as data analytics, machine learning, and scientific computing, are placing an ever-growing demand on floating-point operations per second on emerging systems. With increasing integration density, the quest for energy efficiency becomes the number one design concern. While dedicated accelerators provide high energy efficiency, they are over-specialized and hard to adjust to algorithmic changes. We propose an architectural concept that tackles the issues of achieving extreme energy efficiency while still maintaining high flexibility as a general-purpose compute engine. The key idea is to pair a tiny 10kGE (kilo gate equivalent) control core, called Snitch, with a double-precision floating-point unit (FPU) to adjust the compute to control ratio. While traditionally minimizing non-floating-point unit (FPU) area and achieving high floating-point utilization has been a trade-off, with Snitch, we achieve them both, by enhancing the ISA with two minimally intrusive extensions: stream semantic registers (SSR) and a floating-point repetition instruction (FREP). SSRs allow the core to implicitly encode load/store instructions as register reads/writes, eliding many explicit memory instructions. The FREP extension decouples the floating-point and integer pipeline by sequencing instructions from a micro-loop buffer. These ISA extensions significantly reduce the pressure on the core and free it up for other tasks, making Snitch and FPU effectively dual-issue at a minimal incremental cost of 3.2 percent. The two low overhead ISA extensions make Snitch more flexible than a contemporary vector processor lane, achieving a $2\times$ 2 × energy-efficiency improvement. We have evaluated the proposed core and ISA extensions on an octa-core cluster in 22 nm technology. We achieve more than $6\times$ 6 × multi-core speed-up and a $3.5\times$ 3 . 5 × gain in energy efficiency on several parallel microkernels.

Smart transportation network development with environmental issues into consideration has brought Industry 4.0 based solutions on priority. In this direction, battery-powered electric bus systems have been considered widely for ensuring flexibility, operation cost, and lesser pollutants emission. Industry 4.0 provides automation through a cyber-physical system (CPS), the interconnection of bus system entities with industrial internet-of-things (IIoT), remote information availability through cloud computing and scientific disciplines (human-computer interaction, artificial intelligence, machine learning etc.) integration. In this work, a discrete event-based simulation-optimization approach is integrated that take care of bus energy consumption according to real-time city's passenger needs and on-road friction levels. The proposed simulation optimization methodology utilizes multi-objective with dependent and independent variables for optimizing the overall system performance. In simulation optimization, objective functions are designed to tackle battery consumption, Internet-of-Thing (IoT) network performance, cloud operations efficiency and smart scientific discipline integration. Simulation parameters are based on a real-time bus system which is further analyzed, filtered and adapted as per the needs of the system. In another analysis, supercharger's capacities are varied to evaluate the performance of the proposed system and identify the low cost and efficient smart transportation system. Simulation results show different scenarios for variations in the number of buses, charging stations, bus-depots, mobile charging facilities, and bus-schedules. Simulation results show that the average passenger's waiting time in the waiting is (after ticket booking) varies between 0.2 minutes to 0.7 minutes in real-time traffic conditions. In similar traffic conditions, total passenger's time in system (ticket booking to travel) varies between 41.6 minutes (for 24 hours) to 45.5 minutes (for 1 year). In the simulation, priorities are given to those dependent and independent variables which save the battery consumption and elongate the utilization of buses. Lastly, it is also observed that the proposed system is suitable for resource-constraint devices because Gate Equivalent (GE) calculation shows that the proposed system can be implemented between 1986 GEs (communicational cost without confidentiality and authentication) and 7939 GEs (computational cost with HMAC for authentication in data storage). This ensures varies security primitivs such as confidentiality, availability and authentication.

This paper presents a design of a point scalar multiplier for Edwards curve cryptography (EdCC) based on Edwards25519 curve. For area-efficient implementation, finite field multiplier based on word-based Montgomery multiplication algorithm was designed, and the extended twisted Edwards coordinates system was adopted. The scalar multiplier requires 21,737 gate equivalent and 6.3 kbit RAM. It takes 950,000 clock cycles to calculate scalar multiplication, which is about 6 times faster than ECC processor based on conventional elliptic curves.

Searching the optimal circuit implementation of a Boolean function is still an open problem. This work proposes a new optimizing scheme, which could find circuit expressions with optimal gate equivalent complexity (GEC) using SAT solvers under a depth-L framework. To obtain a better GEC performance in the optimizing scheme, we first propose the ternary and area profile models for SAT problems. The former introduces multiple efficient 3-input logic gates, and the latter takes the different weights of various gates into account in solving. To demonstrate the validity and usefulness, we use our optimizing methodology to search optimized implementation of a given 4-bit S-box with the forced independent property. For an S-box hardware implementation, its forced independent property can ensure that no gate is shared between every two component-circuits, which is beneficial to prevent Differential Fault Analysis (DFA). Finally, we evaluate the implementation performances of two models (i.e., ternary and binary models) and two implementation approaches (i.e., Table-based and Boolean expression methods) by case studies covering several know S-boxes. The experimental results show that our models and approach have better area performance for the S-boxes with forced independence property in most instances.

Due to the rapid growth of using Internet of Things (IoT) devices in the daily life, the need to achieve an acceptable level of security and privacy according to the real security risks for these devices is rising. Security risks may include privacy threats like gaining sensitive information from a device, and authentication problems from counterfeit or cloned devices. It becomes more challenging to add strong security features to extremely constrained devices compared to battery operated devices that have more computational and storage capabilities. We propose a novel application specific instruction-set architecture that allows flexibility on many design levels and achieves the required security level for the Electronic Product Code (EPC) passive Radio Frequency Identification (RFID) tag device. Our solution moves a major design effort from hardware to software, which largely reduces the final unit cost. The proposed architecture can be implemented with 4,662 gate equivalent units (GEs) for 65 nm CMOS technology excluding the memory and the cryptographic units. The synthesis results fulfill the requirements of extremely constrained devices and allow the inclusion of cryptographic units into the datapath of the proposed application-specific instruction set processor (ASIP).

Block ciphers are one of the most fundamental building blocks for information and network security. In recent years, the need for lightweight ciphers has dramatically been increased due to their wide use in low-cost cryptosystems, wireless networks and resource-constrained embedded devices including RFIDs, sensor nodes, smart cards etc. In this paper, an efficient lightweight architecture for RECTANGLE block cipher has been proposed. The architecture is suitable for extremely hardware-constrained environments and multiple platforms due to its support of bit-slice technique. The proposed architecture has been synthesized and implemented on Xilinx Virtex-5 xc5vlx110t-1ff1136 field programmable gate array (FPGA) device. Implementation results have been presented and compared with the existing architectures and have shown commensurable performance. Also, an application-specific integrated circuit (ASIC) implementation of the architecture is done on SCL 180 nm CMOS technology where it consumes 2362 gate equivalent (GE).

The switching transient properties from the switching power semiconductor gate side are sensitive to the device's junction temperature ( $T_{j}$ ). Real-time $T_{j}$ sensing methods based on gate drive switching transient properties have been investigated on silicon MOSFET and silicon IGBT, with a conventional push–pull-type gate drive, under fixed dc-bus voltage. In this paper, this method is applied to silicon-carbide (SiC) MOSFET. The $T_{j}$ sensing methods are evaluated with different types of gate drive topologies. By implementing the SiC MOSFETs into an H-bridge inverter, the effect of dc-bus voltage for the $T_{j}$ sensing method is investigated. Different “gate drive−semiconductor” dynamic models are built, including gate drive output power stage, gate drive parasitics, SiC MOSFET intrinsic parameters, and PCB parasitics. Experimental results are compared with circuit LTSpice model simulation. The device vertical temperature contours are evaluated. Suitable circuitry for $T_{j}$ sensitivity extraction is provided.

SiC MOSFET can operate at a junction temperature of 200–250 $^{\circ }$ C due to its improved material properties and thermal stability. However, successful realization of SiC MOSFET based high-temperature (HT) converter requires HT gate drivers. This paper presents a low-cost HT gate driver developed with discrete transistors and signal diodes rated at 180–200 $^{\circ }$ C. The gate driver has a robust overcurrent and undervoltage lock out protection circuit. The propagation delay of the protection circuit and gate driving circuit is greatly reduced compared to commercial HT gate drivers. A comparative analysis of the developed HT gate driver using discrete components and the commercially available silicon-on-insulator technology based HT gate driver is presented. The performance of the HT gate driver is evaluated for both hard switched fault and fault under load condition at an ambient temperature of 180 $^{\circ }$ C.

In order to enhance specific on-resistance (Ron,sp), the trench gate structure was also introduced into 4H-SiC MOSFET as Si MOSFET. But the 4H-SiC trench gate has worse off-state characteristics than the Si trench gate due to the incomplete gate oxidation process (Simonka et al., 2017). In order to overcome this problem, P-shielding trench gate MOSFET (TMOS) was proposed and researched in previous studies. But P-shielding has to be designed with minimum design rule in order to protect gate oxide effectively. P-shielding TMOS also has the drawback of on-state characteristics degradation corresponding to off state improvement for minimum design rule. Therefore optimized design is needed to satisfy both on and off characteristics. In this paper, the design parameters were analyzed and optimized so that the 4H-SiC P-shielding TMOS satisfies both on and off characteristics. Design limitations were proposed such that P-shielding is able to defend the gate oxide. The P-shielding layer should have the proper junction depth and concentration to defend the electric field to gate oxide during the off-state. However, overmuch P-shielding junction depth disturbs the on-state current flow, a problem which can be solved by increasing the trench depth. As trench depth increases, however, the breakdown voltage decreases. Therefore, trench depth should be designed with due consideration for on-off characteristics. For this, design conditions and modeling were proposed which allow P-shielding to operate without degradation of on-state characteristics. Based on this proposed model, the 1200 V 4H-SiC P-shielding trench gate MOSFET was designed and optimized.

Active gate driving has been demonstrated to beneficially shape switching waveforms in Si- and SiC-based power converters. For faster GaN power devices with sub-10-ns switching transients, however, reported variable gate driving has so far been limited to altering a single drive parameter once per switching event, either during or outside of the transient. This paper demonstrates a gate driver with a timing resolution and range of output resistance levels that surpass those of existing gate drivers or arbitrary waveform generators. It is shown to permit active gate driving with a bandwidth that is high enough to shape a GaN switching during the transient. The programmable gate driver has integrated high-speed memory, control logic, and multiple parallel output stages. During switching transients, the gate driver can activate a near-arbitrary sequence of pull-up or pull-down output resistances between 0.12 and 64 Ω. A hybrid of clocked and asynchronous control logic with 150-ps delay elements achieves an effective resistance update rate of 6.7 GHz during switching events. This active gate driver is evaluated in a 1-MHz bridge-leg converter using EPC2015 GaN FETs. The results show that aggressive manipulation of the gate-drive resistance at sub-nanosecond resolutions can profile gate waveforms of the GaN FET, thereby beneficially shaping the switch-node voltage waveform in the power circuit. Examples of open-loop active gate driving are demonstrated that maintain the low switching loss of constant-strength gate driving, while reducing overshoot, oscillation, and EMI-generating high-frequency spectral content.

Convolutional neural networks (CNNs) have revolutionized the world of computer vision over the last few years, pushing image classification beyond human accuracy. The computational effort of today’s CNNs requires power-hungry parallel processors or GP-GPUs. Recent developments in CNN accelerators for system-on-chip integration have reduced energy consumption significantly. Unfortunately, even these highly optimized devices are above the power envelope imposed by mobile and deeply embedded applications and face hard limitations caused by CNN weight I/O and storage. This prevents the adoption of CNNs in future ultralow power Internet of Things end-nodes for near-sensor analytics. Recent algorithmic and theoretical advancements enable competitive classification accuracy even when limiting CNNs to binary (+1/−1) weights during training. These new findings bring major optimization opportunities in the arithmetic core by removing the need for expensive multiplications, as well as reducing I/O bandwidth and storage. In this paper, we present an accelerator optimized for binary-weight CNNs that achieves 1.5 TOp/s at 1.2 V on a core area of only 1.33 million gate equivalent (MGE) or 1.9 mm 2 and with a power dissipation of 895 $\mu$ W in UMC 65-nm technology at 0.6 V. Our accelerator significantly outperforms the state-of-the-art in terms of energy and area efficiency achieving 61.2 TOp/s/W@0.6 V and 1.1 TOp/s/MGE@1.2 V, respectively.

This paper proposes a new gate driving circuit for the solid-state pulsed power modulator (SSPPM) based on semiconductor devices. The proposed circuit can be easily implemented by applying a short gate signal to the bypass insulated gate bipolar transistor (IGBT), i.e., switches connected in parallel with the load instead of a pull-down resistor. The IGBT_BPs are turned on at the end-point of the pulse. It can quickly discharge the pulse voltage applied to the load. In addition, it can operate as bypass diode, which is used to protect the semiconductor switches when the gate signal malfunctions, by using the antiparallel diode of the IGBT. Moreover, power loss in the pull-down resistor used to achieve fast falling pulses can be eliminated by turning off the IGBT while applying the pulse state. Thus, the proposed circuit can be used for implementing SSPPM with small values of falling time and high efficiency. The circuit configuration, operational principle, relevant analysis results, and a PSpice modeling are presented and verified by the 10-kV SSPPM.

The current era of ubiquitous computing has led to the emergence of a sub-domain in cryptography called Lightweight Cryptography, which deals with imparting adequate security to resource constraint devices like IoT devices, RFID tags with a suitable choice of design metrics. The advancement in network connectivity and data handling capabilities shows the tremendous growth of IoT in physical life. The number of connected devices have been increasing throughout IoT applications, leaving severe security concerns behind. There is a need of secure communication which can be fulfilled with lightweight algorithms. The motive of this work is to implement the optimized lightweight ciphers and model its design metrics. Design has to be simulated to implement the cipher in hardware from which different metrics can be measured. TEA, XTEA and XXTEA ciphers have been used to fulfil the objective stated and were modelled, implemented and optimized on specific hardware technology like Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platform. Designs have been implemented to examine numerous properties like block sizes, rounds of implementations and key scheduling part. This paper presents four hardware architectures namely TEA (T1), XTEA (T2), XXTEA (T3) and hybrid model (T4). T1, T2 and T3 have been implemented using pipelined method with percentage improvement in frequency is 75.9%, 162% and 89%. Similarly, the enhancement in terms of area has been 85.43%, 57.08% and 90.79%. T4 presents a hybrid model which is also a pipelined architecture that combines TEA family (TEA, XTEA and XXTEA) in a single design. The percentage improvement of gate equivalent (GE) for T2 is 47.50%. The hybrid model (T4) has the same throughput as that of T1, T2 & T3 and has less GE when compared to combined GE of all three. Efficiency improvement of all the novel architectures are more than eighteen times as compared to the existing literature.

This paper presents a novel vertical-channel three-dimensional (3-D) NAND flash structure with robust reliability. By employing a more reliable selector, the proposed structure overcomes the key drawback of the conventional 3-D NAND flash which is caused by charge storage in global select gate (GSG) and string select gate (SSG). Based on TCAD simulation, the conventional structure shows a threshold voltage shift of more than 1.5V, while the proposed structure is immune to this issue completely. Key parameters were analyzed to offer guidance on design and fabrication. Thickness of gate dielectric and thickness of SiO2 spacing layer beneath GSG are key parameters for the electrical property of select gate, and thus should be designed accurately.

In this article, we propose the realization of all-optical NAND and NOR logic functions on a single photonic crystal structure by cascading basic logic gates, viz. AND, OR, and NOT. Initially, to achieve this, a photonic crystal logic gate structure is designed with cross-shaped waveguide as a common gate for AND and OR functions, and another photonic crystal structure is devised with T-shaped waveguide as NOT gate. An additional input, namely reference input, is applied to these basic gate structures whose phase determines the type of the logic function in the former gate structure, and inevitable for NOT function in the latter one. The reference input is out of phase with the actual inputs in AND and NOT functions, whereas it is inphase in OR function. Simulation results show that the contrast ratio for AND, OR, and NOT is 11.74, 9.99, and 54.52 dB, respectively, with a response time of less than 0.15 ps. Later, these logic gate structures are cascaded to realize NAND and NOR functions, resulting a contrast ratio of 10.57 and 8.60 dB, respectively, at a response time of 0.152 ps. The percentage of reduction in the contrast ratio of the cascaded structure compared with the basic AND/OR gate is very small with a value of less than 1.5%. Moreover, the proposed NAND/NOR logic gate obtained by cascading the basic logic gates is quite compact with area occupancy lowered by a factor of 4.5 compared to the cascaded structures available in the literature.

Silicon carbide (SiC) and gallium nitride metal–oxide–semiconductor field-effect transistors (MOSFETs) are capable of processing high power at high switching frequencies with less switching losses and conduction losses. The gate driver circuit power consumption is directly proportional to the switching frequency. The power taken from the gate supply is dissipated in the gate resistance of the conventional gate driver (CGD) circuit. Instead of dissipating all the gate driver energy, some energy can be recovered or recycled by utilizing the principle of resonance. This reduces the net power being taken from the gate supply. This paper presents a new resonant gate driver (RGD) circuit which consumes less power compared to the CGD circuit at high switching frequencies. The proposed gate driver is designed for SiC MOSFETs. It can be modified appropriately to suit for insulated-gate bipolar transistors and other MOSFETs also. The performance of the proposed circuit is simulated in LTSpice environment, and an experimental prototype of the proposed circuit is developed to validate its performance. The proposed RGD circuit has achieved nearly 50% reduction in gate driver power consumption compared to the CGD circuit.

This study focused on examining electronic transport through single benzene ring and suggested how such ring can be employed to design XNOR and NAND molecular logic gates. The single benzene ring was threaded by a magnetic flux. The magnetic flux and applied gate voltages were considered as the key tuning parameter in the XNOR and NAND gates operation. All the calculations are achieved by using steady-state theoretical model, which is based on the time-dependent Hamiltonian model. The transmission probability and the electric current are calculated as functions of electron energy and bias voltage, respectively. The application of the anticipated results can be a base for the progress of molecular electronics.

MG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing. In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

A general-purpose clocked gate driver integrated circuit (IC) to generate an arbitrary gate waveform is proposed to provide a universal platform for fine-grained gate waveform optimization handling various power transistors. The fabricated IC with a 0.18 μm Bipolar-CMOS-DMOS process has 63 P-type MOS (PMOS) and 63 N-type MOS (NMOS) driver transistors on a chip whose activation patterns are controlled by 6-bit digital signals and 40 ns time step control. In the 500 V switching measurements with a manual gate waveform optimization, the proposed gate driver reduces the IC overshoot by 25% and 41%, and the energy loss by 38% and 55% for Si-insulated-gate bipolar transistor and SiC-MOSFET, respectively, which demonstrate the feasibility of driving various power devices with the same driver. An automatic optimization by simulated annealing algorithm is introduced to fully utilize the benefit of the gate driver, and the further reduction of IC overshoot by 26% and the energy loss by 18% are achieved over the manual optimization.

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.

Circuit performance of an ultra-thin 3D double gate junctionless nanowire transistor, with an emphasis on digital applications, is investigated. Extensive analysis of inverter circuit and universal gates are performed using mixed mode simulation to understand the characteristics and circuit performance of the device. Different properties, like voltage transfer characteristics, transient response, DC gain, and noise margin of these circuits is studied. Furthermore, to explore the influence of high-K gate dielectrics, we examined circuit performance of the junctionless nanowire device with different gate dielectrics (SiO 2 , Si 3 N 4 , and HfO 2 ). Results show that the devices with high-K gate dielectric (HfO 2 ) have improved circuit performance.

The infrastructure of internet-of-things (IoT) and cyber-physical systems (CPS) is based on the security of communicated data. Here, lightweight cryptography plays a vital role in IoT/CPS resource-constrained environments. In this paper, we propose an architecture for the PRESENT lightweight block cipher and its VLSI implementations in an FPGA and ASIC. The input-output ports of the architecture are registered and datapath is based on 8-bit. It requires 49 clock cycles for processing of 64-bit plaintext with 80-bit user key. The FPGA implementation of the proposed architecture is done in Xilinx Virtex-5 device in comparison to an existing design improved performance has been obtained. Further, an ASIC implementation of the architecture is done in SCL 180 nm technology where gate equivalent (GE) of the design is 1608 GEs and area of chip is 1.55 mm2. At 100 MHz operating frequency, total power consumption of the chip is 0.228 mW. A throughput of 130.612 Mbps, energy 112.15 nJ, energy/bit 14.018 nJ/bit, and 0.813 efficiency is obtained.

This paper presents a modified low-voltage MOS current mode logic (MCML) exclusive-OR (XOR) gate. The proposed topology introduces multiple threshold voltage transistors in the triple-tail cell of a MCML XOR gate. This scheme allows reduction in the implementation area of a triple-tail cell and the logic gate employing it. The impact of employing multiple threshold voltage transistors on the operation of the XOR gate is investigated; and mathematical formulations for the static and delay parameters are derived. A design procedure based on the static model is put forward. The accuracy of the models is verified by designing and simulating the proposed XOR gate for wide operating conditions. The model parameters of TSMC 0.18m CMOS technology are used. An assessment in terms of implementation area and the process variations is conducted for the proposed and the available XOR gates. Finally, the performance of all the XOR topologies is compared for different design cases and the favorable cases are identified.

This paper presents a gate driver with fast switching and low switching loss for silicon carbide-metal oxide semiconductor field effect transistors. The proposed driver consists of a very simple gate boost circuit and a speed up circuit, and so is cost-effective. Normally, conventional gate drive methods include a trade-off between switching losses and noise. The proposed gate driver can reduce switching losses without increasing surge voltage as well as voltage and current fluctuations. The proposed gate driver is able to eliminate the trade-offs in the switching characteristics.

Metal gate/high-k stacks are in CMOS manufacturing since the 45 nm technology node. To meet technology performance and yield targets, gate stack reliability is constantly being challenged. Assessing the associated reliability risk for CMOS products relies on a solid understanding of device to circuit reliability correlations. In this paper we summarize our findings on the correlation between device reliability and circuit degradation and highlight areas for future work to focus on.

In a continuous effort to increase the DC and RF figure-of-merits (FOMs), multigate MOSFETs have evolved from classical planar device into a gate all around structure. The unique design with accuracy in device performance has made it a cutting edge device to overcome the scaling and performance barrier of the present VLSI technology. The fabrication process of a surface channel device with proper threshold voltage (Vth) directly depends upon the work-function of the gate electrode. By keeping it in mind, a metal gate with linearly modulated work-function (5–4.2 ev) along the z-axis in a cylindrical surrounding gate MOSFET is introduced. This work demonstrates the potential benefits of work-function modulation based dual material cylindrical gate MOSFET (WMDMCG) in terms of DC performance characteristics. The present model provides improved DC performance as compared to conventional dual material cylindrical surrounding gate MOSFET (DMCG) and the results obtained are validated with TCAD device simulator from Synopsys.

This work optimizes the gate engineering scheme (both gate stack and gate metal workfunction engineering) of Stacked Gate (SG) Gate Electrode Workfunction Engineered (GEWE)-Silicon Nanowire MOSFET at 300 K for improved analog and intermodulation performance. This has been done by evaluating and analyzing the metrics such as Switching Ratio, Subthreshold Swing (SS), Device Efficiency, channel and output resistance, VIP3, IIP3, 1-dB Compression Point, IMD3, HD2 and HD3. Simulation results exhibit that HfO2 as a gate stack exhibit high linearity at a comparatively low gate bias of 0.56 V with higher IIP3 (6.21 dBm) and low IMD3 (9.6 dBm). Further, the characteristics/performance is modulated by adjusting the workfunction difference of metal gate. This study demonstrates that SiNW MOSFET modeled with HfO2 as a gate stack over SiO2 interfacial layer, and gate metal workfunction difference (ΔW) of 4.4 eV can be considered as a promising potential for low power switching component in ICs and Linear RF amplifiers.

This paper presents an energy-recycling class-D low-side gate driver integrated circuit (IC), which can also perform 5-to-15-V level upconversion using a bidirectional flyback converter topology. The gate driver itself is a mini switching regulator that operates at 5–15 MHz to generate 1-μs transition time gate-switching waveforms. In order to maintain uniform charging/discharging currents during transitions, the embedded flyback converter operates in a pulse-frequency modulation mode while charging and in a pulse width modulation mode while discharging the gate node. The required pulses with digitally programmable frequencies and duty cycles are efficiently generated by a custom-designed IC fabricated in a 0.25-μm HV CMOS technology. Also, the presented analysis guides a way to achieve the desired transition time with the maximum efficiency. The prototype IC demonstrates 37.5% energy recycling while driving a 15-V insulated-gate bipolar transistor power switch with 105-nC gate charge at 20 kHz.

In this paper we proposed a new design for all optical NAND gate. By combining nonlinear Kerr effect with photonic crystal ring resonators, we designed an all optical NAND gate. A typical NAND gate is a logic device with one bias and two logic input and one output ports. It has four different combinations for its logic input ports. The output port of the NAND gate is OFF, when both logic ports are ON, otherwise the output port will be ON. The switching power threshold obtained for this structure equals to 1.5 kW/μm 2 . For designing the proposed optical logic gate we employed one resonant ring whose resonant wavelength is at 1554 nm. The functionality of the proposed NAND gate depends on the operation of this resonant ring. When the power intensity of optical waves is less than the switching threshold the ring will couple optical waves into drop waveguide otherwise the optical waves will propagate on the bus waveguide.

A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual-outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin-film-transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5-inch Full HD (1080xRGBx1920) TFT-liquid-crystal display panel and passed reliability tests of the supporting foundry.

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of "AND" gate and can be extended to full functionality of 2-input digital "NAND" gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as "NAND" gate even at low operating voltage.

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green’s functions (NEGF) solved self - consistently with Poisson’s equations. It is revealed that hetero -material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of Ф M1 /Ф M2 have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow.

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

The design of ultra-low power advanced encryption standard (AES) encryption cores for emerging wireless networks and Internet of things systems by combining optimised architectures, a simple clock gating technique and an advanced 65 nm silicon on thin buried oxide (SOTB) CMOS process is presented. The implementation results show that the proposed 2-Sbox AES encryption core requires the smallest number of clock cycles and achieves the lowest power consumption of 0.4 µW/MHz which is 3.3× lower than that of the best previous presented AES encryption core, with a very small area overhead. Moreover, the proposed 1-Sbox AES encryption core consumes very low hardware resources of 2.4 kgates gate equivalent.

A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing the proposed gate engineering concept are designed and simulated. Engineered gate N-type MOS and P-type MOS are used for PD and pull-up circuits, respectively. Since only two devices are used for a complete circuit: one in PU network and other in PD network; therefore, area and power of the proposed circuits get reduced significantly in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it can be extended to realise other combinational and sequential circuits easily.

The paper proposes a new lightweight encryption design DoT which supports block length of 64 bits with a key size of 80/128 bits. DoT is the 31-round substitution and permutation-based network. Hardware and software parameters are the main key focused for designing the DoT cipher, and DoT cipher shows the good performance on both hardware and software. The metrics which makes the DoT efficient as compared to other lightweight ciphers are memory size, Gate Equivalent (GEs) and throughput. DoT cipher design results in only 2464 bytes of flash memory, and it needs only 993 GEs for its hardware implementation. While considering the speed of the DoT cipher with block input of 64 bit, it gives 54 Kbps which is very much greater than other existing ciphers. DoT design consists of a single S-box, few shift operators and a couple of XOR gates. We believe that DoT is the compact and smallest cipher till date for GEs, memory requirement and execution time.

Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. This paper introduces a novel Vertical Slit Field Effect Transistor with unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits. A new adder circuit is proposed, where the power could be reduced by one fifth and the area by on third compared to a tied gate configuration.

In this paper, we report the 2-D drain current model for asymmetric dual material (DM) junctionless double gate transistor. On the basis of channel potential, transconductance and its higher order derivatives are estimated and verified with the ATLAS 3-D device simulator results. The developed model is also applicable to investigate the digital performance of the device in terms of voltage transfer characteristics of nMOS inverter circuit. The impact of the length of control gate on the analog performance has also been investigated. Results also highlight the advantage of DM gate over the single material gate for digital and analog applications using CMOS inverter and common source amplifier through exhaustive circuit simulation.

This paper presents a novel and simple integrated gate driver circuit composed of only four thin-film transistors (TFTs) and three capacitors for slim-border and high-resolution applications. The input TFT has multi-functions to reduce the components of the circuit and its driving capability is enhanced to improve the rising time of the output waveform, so the size of the input TFT can be decreased. Moreover, the large-size pullup TFT is also used to discharge the row line for decreasing the falling time of the output waveform, so that an additional largesize pull-down TFT can be eliminated for further diminishing the circuit area. Importantly, an inverse-coupling method is introduced to suppress the noise of the row line, which can also lessen the number of TFTs and simplify the circuit structure.

Reversible logic concept gaining much attention of researchers due to its characteristics of generating loss-less system. Reversible logic technology do not erase information hence no heat dissipation. In this paper a new reversible SMT logic gate has been proposed .The proposed three inputs, three outputs reversible logic based SMT gate has designed for Logical, Boolean and Arithmetical functions. This gate needs only one clock cycle to perform multifunctional operation and produce no garbage output. In the present investigation reversible half adder and half subtractor gate has been successfully realized by SMT gate. It produces zero garbage outputs. The proper coding proves that the proposed gates are fulfilling the requirement of reversible logic gate. In present paper different properties of SMT gate has been simulated using VHDL.

While floating-gate MOS transistor in mixed-signal applications have been studied in the literature, little has been reported on modeling them with gate leakage current (GLC). This paper presents a simulation model for floating-gate MOS transistor in nanometer-scale technologies. The proposed model accounts for direct tunnelling GLC in sub 3 nm gate oxide thickness. The model can be used for both transient and DC simulations with any industry standard simulators. HSPICE simulations and measurements of an experimental chip using TSMC 90 nm technology were presented.

Silicon-Carbide (SiC) MOSFETs, due to material properties, are designed with smaller thickness in the gate oxide and a higher electric field compared to Si MOSFETs. Consequently, the SiC MOSFETs have a worse reliability which causes higher leakage currents during instantaneous abnormal operating conditions. This paper investigates the reliability issues of the SiC MOSFET gate oxide under standard short-circuit test conditions. In this paper, 1200-V SiC MOSFETs are newly modeled, and also their short-circuit sustainability (tolerance) have been studied at different drain-source and gate-source voltages. A hardware tester circuit was designed and developed to test the devices under such extreme circuit conditions. Then, the gate reliability of SiC MOSFET devices have been compared to that of Si power devices of similar ratings. The results reveal a higher reduction in the instantaneous gate-source voltage of SiC MOSFETs compared to that of Si devices under the same operating conditions. The gate-voltage reduction phenomenon results from the higher leakage currents through the gate. Furthermore, it was found that the gate-source voltage reduction during the test depends on the gate structures. The gate voltage reduction of SiC MOSFETs with planar gate is higher than that of MOSFETs with shield planar gate. As the pulse duration increases in short-circuit tests, the leakage current in the gate-source of SiC devices increases. The results show that even though the SiC MOSFETs are very capable of processing long pulses and high power in the drain-source, the gate-source side is highly degraded by these pulses in the test. Moreover, whenever a small number of the short-circuit tests are applied, the gate structure of SiC MOSFETs becomes broken while the drain-source is still able to block the dc-link voltage. The paper concludes that the short-circuit reliability of the gate was found to be worse compared with commercial Si devices with similar rating.

This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations .in this paper two bit addition has been done using conventional and transmission gate level and power, area and number of transistors are the scope of comparison. According to the simulation result, power and area are reduced by 55.35 % and 40.269% respectively when the circuit is implemented by transmission gate .thus transmission gate has become a very popular and useful technique to implement digital circuits which help to reduce power, surface area as well as number of transistors.

2 Abstract: Duty-cycle correctors are widely used in high-speed devices and system-on-a-chip applications. Because both the positive and negative edges of the clock are utilized for sampling the input data, these systems require an exact 50% duty cycle of the input clock. However, as the clock signal is distributed over the entire chip with clock buffers, the duty cycle of the clock is often far from 50%. Because of the unbalanced rise and fall times, as a result of variations in process, voltage, and temperature. To resolve this problem and to correct the duty-cycle error many approaches are presented. In this work, wide-range NAND gate based glitch-free all-digital duty-cycle corrector is presented. The proposed NAND gate based glitch-free ADDCC not only achieves the desired output/input phase alignment, but also maintains the output duty cycle at 50% with a short locking time. In addition, the proposed method can mitigate the delay mismatch problem and produce minimum delay without any glitch. The circuit complexity also is reduced in the proposed NAND gate based ADDCC. The simulation is carried out in 0.65 nanometer CMOS process. An experimental result shows that the power consumed, delay and area is reduced in the proposed architecture. Simulation results are obtained using MODELSIM 6.3f. The power, area and delay are obtained using the XILINX ISE 8.1 software.

This paper presents the analysis and design of an electronic failure detection system applied to the insulated gate bipolar transistor (IGBT), this proposal is based on the direct measurement of behavior of the gate signal during the turn-on transient. The failures by short-circuit and open-circuit devices only are considered in this paper. To achieve early detection, the IGBT gate signal behavior during turn-on transient is used and to increase the effectiveness of the detection and to tolerate the variations of input to system, adaptable thresholds have been added to the analog electronics circuit implemented. The experimental tests are presented in order to validate the proposed fault-detection technique.