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We extend the offline memory correctness checking scheme presented by Blum et. al [BEG+91], by using incremental cryptography, to detect attacks by an active adversary. We also introduce a hybrid o_ine-online checking scheme designed for untrusted storages in file systems and databases. Previous work [GSC+02] [FKM00] [MVS00] describe systems in which Merkle trees are used to verify the authenticity of data stored on untrusted storage. The Merkle trees [Mer79] are used to check, after each operation, whether the storage performed correctly. The offline and hybrid checkers are designed for checking sequences of operations on an untrusted storage and, in the common case, require only a constant overhead on the number of accesses to the storage, as compared to the logarithmic overhead incurred by online Merkle tree schemes

We describe the architecture for a single-chip AEGIS processor which can be used to build computing systems secure against both physical and software attacks. Our architecture assumes that all components external to the processor, such as memory, are untrusted. We show two different implementations. In the first case, the core functionality of the operating system is trusted and implemented in a security kernel. We also describe a variant implementation assuming an untrusted operating system. AEGIS provides users with tamper-evident, authenticated environments in which any physical or software tampering by an adversary is guaranteed to be detected, and private and authenticated tamper-resistant environments where additionally the adversary is unable to obtain any information about software or data by tampering with, or otherwise observing, system operation. AEGIS enables many applications, such as commercial grid computing, secure mobile agents, software licensing, and digital rights management. We also present a new encryption/decryption method that successfully hides a significant portion of encryption/decryption latency, in comparison to a conventional direct encryption scheme. Efficient memory encryption and integrity verification enable the implementation of a secure computing system with the only trusted component being a single-chip AEGIS CPU. Preliminary simulation results indicate that the overhead of security mechanisms in AEGIS is reasonable.

Memory integrity verification is a useful primitive when implementing secure processors that are resistant to attacks on hardware components. This paper proposes new hardware schemes to verify the integrity of untrusted external memory using a very small amount of trusted on-chip storage. Our schemes maintain incremental multiset hashes of all memory reads and writes at run-time, and can verify a {\\em sequence} of memory operations at a later time. We study the advantages and disadvantages of the two new schemes and two existing integrity checking schemes, MACs and hash trees, when implemented in hardware in a microprocessor. Simulations show that the new schemes outperform existing schemes of equivalent functionality when integrity verification is infrequent.

In general, secure protocols assume that participants are able to maintain secret key information. In practice, this assumption is often incorrect as an increasing number of devices are vulnerable to physical attacks. Typical examples of vulnerable devices are smartcards and Automated Teller Machines. To address this issue, Physical Random Functions are introduced. These are Random Functions that are physically tied to a particular device. To show that Physical Random Functions solve the initial problem, it must be shown that they can be made, and that it is possible to use them to provide secret keys for higher level protocols. Experiments with Field Programmable Gate Arrays are used to evaluate the feasibility of Physical Random Functions in silicon.

We describe the architecture of the AEGIS processor which can be used to build computing systems secure against both physical and software attacks. AEGIS assumes that the operating system and all components external to it, such as memory, are untrusted. AEGIS provides tamper-evident, authenticated environments in which any physical or software tampering by the adversary is guaranteed to be detected, and private and authenticated, tamper-resistant environments where additionally the adversary is unable to obtain any information about software or data by tampering with, or otherwise observing, system operation. AEGIS enables many applications, such as commercial grid computing, software licensing, and digital rights management. We present a new encryption/decryption method that successfully hides a significant portion of encryption/decryption latency, in comparison to a conventional direct encryption scheme. Efficient memory encryption and integrity verification enable the implementation of a secure computing system with the only trusted component being a single-chip AEGIS CPU. Detailed simulation results indicate that the performance overhead of security mechanisms in AEGIS is reasonable.

AEGIS is a single-chip secure processor that can be used to protect the integrity and confidentiality of an application program from both physical and software attacks. We briefly describe the history behind this architecture and its key features, discuss main observations and lessons from the project, and list limitations of AEGIS and how recent research addresses them.

We report the fabrication and experimental characterization of a novel low-cost carbon nanotube (CNT)-based electron impact ionizer (EII) with integrated gate for portable mass spectrometry applications. The device achieves low-voltage ionization using sparse forests of plasma-enhanced chemical vapor deposited (PECVD) CNTs field emitter tips, and a proximal gate with open apertures to facilitate electron transmission. The gate is integrated using a deep reactive ion etched (DRIE) spring-based high-voltage MEMS packaging technology. The device also includes a high aspect-ratio silicon structure (mufoam) that facilitates sparse CNT growth and limits the electron current per emitter. The devices were tested as field emitters in high vacuum (10-8 Torr). Electron emission starts at a gate voltage of 110 V, and reaches a current of 9 uA at 250 V (2.25 mW) with more than 55% of the electrons transmitted through the gate apertures. The devices were also tested as electron impact ionizers using argon. The experimental data demonstrates that the CNT-EIIs can operate at mtorr-level pressures while delivering 60 nA of ion current at 250 V with about 1% ionization efficiency.

We report the fabrication and experimental characterization of a carbon nanotube (CNT)-based MEMS/NEMS electron impact gas ionizer with an integrated extractor gate for portable mass spectrometry. The ionizer achieves low-voltage ionization using sparse forests of plasma-enhanced chemical-vapor-deposited CNTs as field emitters and a proximal extractor grid with apertures aligned to the CNT forests to facilitate electron transmission. The extractor gate is integrated to the ionizer using a high-voltage MEMS packaging technology based on Si springs defined by deep reactive ion etching. The ionizer also includes a high-aspect-ratio silicon structure (??foam) that facilitates sparse CNT growth and also enables uniform current emission. The devices were tested as field emitters in high vacuum (10[superscript -8] torr) and as electron impact ionizers using argon at pressures of up to 21 mtorr. The experimental data show that the MEMS extractor gate transmits up to 66% of the emitted current and that the ionizers are able to produce up to 0.139 mA of ion current with up to 19% ionization efficiency while consuming 0.39 W.

This paper reports the design and fabrication of high-aspect-ratio needlelike silicon structures that can have complex geometry. The structures are hundreds of micrometers tall with submicrometer-sharp protrusions, and they are fabricated using a series of passivated and unpassivated deep reactive-ion etching (DRIE) steps. A simple model is presented to predict the geometry of the structure based on the etch mask and the etch sequence. Model predictions are in good qualitative agreement with fabrication results, making it a useful design tool. The model is compared with literature reports on tapered DRIE., United States. National Aeronautics and Space Administration (Space and Naval Warfare Systems Center Award N66001-04-1-8925), Space and Naval Warfare Systems Center San Diego (U.S.) (Award N66001-04-1-8925), United States. Army (Soldiers Systems Command Award W911QY-05-1-0002)

This paper reports the design, fabrication, and experimental characterization of a fully microfabricated planar array of externally fed electrospray emitters that produces heavy molecular ions from the ionic liquids EMI-BF[subcript 4] and EMI-Im. The microelectromechanical systems (MEMS) electrospray array is composed of the following two microfabricated parts: 1) an emitter die with as many as 502 emitters in 1.13 cm[superscript 2] and 2) an extractor component that provides assembly alignment, electrical insulation, and a common bias voltage to the emitter array. The devices were created using Pyrex and silicon substrates, as well as microfabrication techniques such as deep reactive ion etching, low-temperature fusion bonding, and anodic bonding. The emitters are coated with black silicon, which acts as a wicking material for transporting the liquid to the emitter tips. The extractor electrode uses a 3-D MEMS packaging technology that allows hand assembly of the two components with micrometer-level precision. Experimental characterization of the MEMS electrospray array includes current-voltage characteristics, time-of-flight mass spectrometry, beam divergence, and imprints on a collector. The data show that with both ionic liquids and in both polarities, the electrospray array works in the pure ionic regime, emitting ions with as little as 500 V of bias voltage. The data suggest that the MEMS electrospray array ion source could be used in applications such as coating, printing, etching, and nanosatellite propulsion., Devadas, Srinivas, United States. Air Force Office of Scientific Research, Space and Naval Warfare Systems Center San Diego (U.S.) (Award N66001-04-1-8925), United States. Defense Advanced Research Projects Agency. Microsystems Technology Office and U.S. Army Soldier and Biological Chemical Command. Soldier Systems Center (Contract W911QY-05-1-0002)

This paper reports the design and experimental validation of an in-plane assembly method for centimeter-scale bulk-microfabricated components. The method uses mesoscaled deep-reactive-ion-etching (DRIE)-patterned cantilevers that deflect and lock into small v-shaped notches as a result of the hand-exerted rotation between the two components of the assembly. The assembly method is intended for MEMS arrays that necessitate a 3-D electrode structure because of their requirement for low leakage currents and high voltages. The advantages of the assembly method include the ability to decouple the process flow of the components, higher overall device yield, modularity, reassembly capability, and tolerance to differential thermal expansion. Both tapered and untapered cantilevers were studied. Modeling of the cantilever set shows that the springs provide low stiffness while the assembly process is in progress and high stiffness once the assembly is completed, which results in a robust assembly. In addition, analysis of the linearly tapered cantilever predicts that the optimal linearly tapered beam has a cantilever tip height equal to 37% of the cantilever base height, which results in more than a threefold increase in the clamping force for a given cantilever length and deflection, compared to the untapered case. The linear taper profile achieves 80% of the optimal nonlinear taper profile, which would be impractical to fabricate. Analysis of the experimental data reveals a biaxial assembly precision of 6.2-mum rms and a standard deviation of 0.6 mum for assembly repeatability. Electrical insulation was investigated using both thin-film coatings and insulating substrates. Leakage currents less than 1 nA at 2 kV were demonstrated. Finally, this paper provides selected experimental data of a gated MEMS electrospray array as an example of the application of the assembly method., United States. Air Force Office of Scientific Research, Space and Naval Warfare Systems Center San Diego (U.S.) (Award N66001-04-1-8925)

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007., This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections., Includes bibliographical references (p. 257-269)., This thesis presents the design, fabrication and testing of a fully-integrated planar electrospray thruster array, which could lead to more efficient and precise thrusters for space propulsion applications. The same techniques could be used for making arrays to increase throughput in many other electrospray applications. Electrospray thrusters work by electrostatically extracting and accelerating ions or charged droplets from a liquid surface to produce thrust. Emission occurs from sharp emitter tips, which enhance the electric field and constrain the emission location. The electrospray process limits the thrust from a single tip, so that achieving millinewton thrust levels requires an array with tens of thousands of emitters. Silicon batch microfabrication has been used, as it is well suited for making large arrays of emitters. The thruster is made using Deep Reactive Ion Etching (DRIE) and wafer bonding techniques, in a six mask process, and comprises two components. The emitter die with up to 502 emitters in a 113 mm2 area, is formed using DRIE and SF6 etching, and is plasma treated to transport liquid to the tips in a porous black-silicon surface layer. The extractor die incorporates the extractor electrode, a Pyrex layer for insulation, and springs which are used to reversibly assemble the emitter die. This versatile assembly method, with 10 µm RMS alignment accuracy and 1.3 µm RMSD repeatability, allows the extractor die to be reused with multiple emitter dies, and potentially with different emitter concepts than the one presented. The thruster, weighing 5 g, was tested with the ionic liquids EMI-BF4 and EMIIm. Time of flight measurements show that the thruster operates in the ion emission regime most efficient for propulsion, with a specific impulse around 3000 s at a 1 kV extractor voltage. Emission starts as low as 500 V. Currents of 370 nA per emitter have been recorded at 1500 V, for an estimated thrust of 26 nN per emitter or 13 µN total, and a 275 mW po, by Blaise Laurent Patrick Gassend., Ph.D.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003., This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections., Includes bibliographical references (p. 87-89)., In general, secure protocols assume that participants are able to maintain secret key information. In practice, this assumption is often incorrect as an increasing number of devices are vulnerable to physical attacks. Typical examples of vulnerable devices are smartcards and Automated Teller Machines. To address this issue, Physical Random Functions are introduced. These are Random Functions that are physically tied to a particular device. To show that Physical Random Functions solve the initial problem, it must be shown that they can be made, and that it is possible to use them to provide secret keys for higher level protocols. Experiments with Field Programmable Gate Arrays are used to evaluate the feasibility of Physical Random Functions in silicon., by Blaise L.P. Gassend., S.M.

Knowledge flow analysis offers a simple and flexible way to find flaws in security protocols. A protocol is described by a collection of rules constraining the propagation of knowledge amongst principals. Because this characterization corresponds closely to informal descriptions of protocols, it allows a succinct and natural formalization; because it abstracts away message ordering, and handles communications between principals and applications of cryptographic primitives uniformly, it is readily represented in a standard logic. A generic framework in the Alloy modelling language is presented, and instantiated for two standard protocols, and a new key management scheme.