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The detection of EUV mask adder defects has been investigated with an optical wafer defect inspection system employing a methodology termed Die-to-“golden” Virtual Reference Die (D2VRD). Both opaque and clear type mask absorber programmed defects were inspected and characterized over a range of defect sizes, down to (4x mask) 40 nm. The D2VRD inspection system was capable of identifying the corresponding wafer print defects down to the limit of the defect printability threshold at approximately 30 nm (1x wafer). The efficacy of the D2VRD scheme on full chip wafer inspection to suppress random process defects and identify real mask defects is demonstrated. Using defect repeater analysis and patch image classification of both the reference die and the scanned die enables the unambiguous identification of mask adder defects.

This paper presents a systematic methodology to enable Puma double dark field wafer inspection tool to detect key yield related defect that causes micro-masking defects in the Gate module/sector of an advanced 32nm High-K Metal Gate (HKMG) SOI technology device. Two approaches were adapted to detect the source of the micro-masking defect, namely (i) Patterned wafer inspection in High K metal Gate module to understand the initial findings (ii) Collaborative work with other advanced fabs (Partners) that led to a systematic partitioning approach through the Front End of the Line (FEOL) sectors to exactly pinpoint the root cause of the yield loss in Gate sector. Based on the above systematic partitioning approach, the source of the embedded defect that causes yield loss in gate sector was successfully identified. This methodology has also enabled a process fix to be put in place for reducing the addition of embedded defects in the FEOL sector and has directly helped in improving the yield in FEOL sector. This paper also discusses the advantage of collaborating with different wafer manufacturing companies (IBM partners) in being able to successfully identify root cause of key yield limiting issues.

As lithographers continue to implement more exotic and complex Resolution Enhancement Techniques (RET) to push patterning further beyond the physical limits of optical lithography, full-chip brightfield inspections are be-coming increasingly valuable to help identify random and systematic defects that occur due to mask tolerance ex-cursions, OPC inaccuracies, RET design errors, or unmanufacturable layout configurations. PWQ, or Process Window Qualification, is a KLA-Tencor product* using brightfield imaging inspection technology that has been developed to address the need for rapid full-chip process window verification. PWQ is currently implemented at IBM"s 300mm facility and is being used to isolate features that repeatedly fail as a function of exposure dose and focus errors. We will demonstrate how PWQ results have assisted in: 1) qualification of reticles and new OPC models; 2) identification of non-obvious lithographic features that limit common process windows; 3) providing input for long-term design for manufacturability (DfM), OPC, and/or RET modeling. PWQ allows full or partial chips to be scanned in far less time than a multi-point common process window collected on a SEM. PWQ findings supplement these traditional analysis methods by encompassing all features on a chip, providing more detail on where the process window truly lies. Examples of marginal features that were detected by PWQ methods and their subsequent actions will be discussed in this paper for an advanced 65nm and a 90nm CMOS process.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.