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Due to the flourishing development of the Internet of Things (IoT) technology, many smart home applications have become commercially available. One of the most popular applications is remotely controlled smart sockets. Most commercial smart socket products allow the user to control single-sockets. This paper proposes a smart socket system called MorSocket (“more sockets”) that allows the user to control multiple separated sockets within a control webpage. These sockets share the same wireless communication module and therefore the hardware cost of MorSocket is lower than the single-socket solutions. Furthermore, by integrating MorSensor with an IoT management platform called IoTtalk, MorSocket can be automatically controlled by arbitrary sensors for temperature, humidity, UV, CO2, and so on. Such configuration is easily and flexibly set up through the IoTtalk GUI without extra programming efforts. We also develop the MorSensor system that provides multiple configurable sensors tailored to control MorSocket through simple plug-and-play. Then we investigate the user tolerance delay between when the user presses the on/off button and when he/she presses the next time if MorSocket does not respond. The user experience is poor if the MorSocket access delay is longer than the tolerance delay, and the user may keep pressing the button. We conduct measurements, analytic modeling, and simulation experiments to study the impact of the user tolerance delay. Our study observes the quick response of MorSocket, which results in excellent user experience.

The traditional SOMA cube is a solid dissection puzzle and an educational toy. However, to complete assembly SOMA cube is a difficult challenge for most children and even adults. In this paper, we developed smart electronic intelligent SOMA (iSOMA) blocks that can self-detect each other’s position and contact surface. We also have developed an interactive gaming system based on virtual interactive technology. This interactive gaming system can quickly teach children how to quickly assemble iSOMA blocks and let them learn math and geometry problems through the game. This technology, in addition to being used in assembling puzzles, can also be used in the assembly of real objects in life.

Scour around bridge pier is a major cause of bridge failure such as collapse resulted in loss of life and property. Most of available sensors and approaches for monitoring bridge pier scour are very expensive, which is a main challenge for mass deployment of numerous bridges. Our proposed scour monitoring system utilized low-cost commercial sensors, hall-effect sensors (unit price< $1) that are capable of real-time measuring bridge pier scour with resolution of ~ 2.5 cm, and overall cost for single sensor node of our proposed work is at least 40 % less expensive than existing work. The hall- effect sensor is evaluated under controlled conditions in two laboratory flumes. After scour event, the typical voltage change of the hall-effect sensor is ~ 300 mV, and the system achieve signal-to-noise ratio performance of ~ 60 dB. Finally, we also provide an equation to predict the time variation of scour depth around pier model. Moreover, the master-slave architecture of bridge pier scour monitoring system has scalability and flexibility for mass deployment. This technique has the potential for further widespread implementation in the field.

SUMMARY This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18µm CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.

This work investigates a power line communication (PLC) in a DC power management system comprising master-slave control networks. Microcontroller-based master and slave units are designed with serial ports for communication with a controller and a transmission port to couple the signal to modems at both ends. However, coupling data signals to power line through modulation interfacing circuits is a challenging task. In this work, we used time-division multiplexing (TDM) technique to divide into two timings, Powering Time and Communication Time, on the DC power line and can reduce the complexity of the master-slave network and noise effect on the power line.

This paper presents a FlexRay Transceiver (FRT) with Bus Guardian (BG) used in an in-vehicle network compliance with FlexRay physical layer standards. FlexRay is a new standard for data/signal communication among electronic devices installed in a vehicle. The FRT includes two major parts in the physical layer design: the data transmission part, i.e., Bus Driver (BD), which is used to generate and recognize the electrical characteristics on the bus; the control part, including Bus Driver Controller and Bus Guardian (BG), which is in charge of data path, security, safety, and supervising Communication Controller (CC) in FlexRay communication systems. The proposed FRT with BG design in this work is implemented using a typical 0.18 μm CMOS process. The total core area is 0.88 × 0.84 mm2 and the power consumption is 53.04 mW at a 80 MHz system clock by physical on-silicon measurement.

This paper presents a FlexRay Transceiver (FRT) used in an in-vehicle network compliant with FlexRay physical layer standards. FlexRay is a new standard for data/signal communication among ECUs (electronic control unit) installed in a vehicle. FRT at least comprises two major blocks in the physical layer design: the data transmission block, i.e., Bus Driver (BD), which is used to generate signals on the bus and recognize the signal electrical characteristics on the bus; and the control block, i.e., Major Controller, which is in charge of data path, security, and safety. The proposed FRT design in this work is implemented using a typical [email protected] CMOS process. The total core area is 1.01x0.894mm^2 and the power consumption is 76.62mW at a 80MHz system clock.

This paper presents a DC-DC step-down converter, which can accommodate the range of power supply voltage from VDD to sub-2xVDD. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the proposed design is realized by a typical 1P6M 0.18@mm CMOS process without using any high voltage process to resolve gate-oxide reliability and leakage current problems. The core area of the proposed design is less than 0.184mm^2, while the power supply range is up to 5V. Since the internal reference voltage is 1.0V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of battery-based power supply. Therefore, it can be integrated in a SOC (system-on-chip) to provide multiple supply voltage sources.

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.

This paper presents an in-car networking transceiver front end that is compliant with FlexRay automotive electronic standards. A low-voltage differential-signaling-like transmitter is proposed to drive the twisted pair of the bus. Furthermore, a three-comparator scheme is used to carry out bit slicing and state recognition at the receiver end. In order to resist process and temperature variation, a 20-MHz clock generator with process, supply voltage, and temperature compensation is proposed in this paper. A prototype system as well as a chip implemented by using a typical 0.18 ?m single-poly six-metal CMOS process is reported in this paper. The proposed prototypical transceiver front end has been tested by the thermo chamber and a FlexRay development board to certify its operation in the [-40°C-+125°C] temperature range and FlexRay standards. The power consumption of the whole chip is 43.01 mW at a 10 Mbit/s throughput. The core area of this design is 0.117 mm2. The maximal throughput of the proposed prototypical transceiver front end can reach 40 Mbit/s.

This paper presents the architecture as well as the circuit implementation of a wireless personal area networks (WPAN) modulator/demodulator using 2.45GHz band compliant with the physical layer standard of IEEE 802.15.4. A noncoherent demodulation scheme is employed to resolve the complexity and power dissipation problem, where a phase-shift down sampling method is adopted to detect the maximum phase accumulation which is the location of the correct data. A prototypical system on silicon with core area of 0.39mm^2 has been realized by using 0.18@mm CMOS process. The packet error rate (PER) is measured to be

This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions as well as computations when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing method. Thorough post-layout simulations of a 8×8 digital multiplier using the proposed 2-dimensional bypassing method show that the power dissipation of the proposed design is reduced by more than 75% compared to prior designs. Physical measurements on silicon reveal that the proposed digital multiplier saves more than 28% even with pads' power dissipation compared to the prior works.

The design of a 1.7-ns access time prototype CMOS SRAM is presented. The threshold voltages of the wordline-controlled transistors (WCT) of the proposed memory cells are dynamically variable to achieve high-speed and low-power operations. When the cell is in the read or write (R/W) mode, the VTH of the wordline-controlled transistors is pulled low by increasing the bulk bias such that the drain current will be increased. By contrast, if it is idle in a standby mode, the bulk bias will be reduced by short-circuiting to a ground voltage to subside the leakage current. The highest operating clock rate of the proposed SRAM is measured to be 667 MHz. Moreover, the proposed memory cell possess high stability, the static noise margin is close to 635 mV given the worst case (75°C, FF model, VDD = 1.6 V ).

A high speed and low-power 8-bit carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. The analysis of the area (transistor count) tradeoff is also provided in this work. The output of the addition of two 8-bit binary numbers is done in two cycles. The proposed power-aware pipelining design methodology using a simple data transition detection circuit takes advantage of shutting down the processing stages with identical inputs in two consecutive cycles. The data transition detection circuit is used to monitor the state switching of input data. Not only is it proved to be also suitable for long adders, the power consumption is drastically reduced by at most 50% at every process corner.

This paper presents a design of a 72.7ps peak-to-peak (p2p) jitter, 80MHz, phase-locked loop (PLL) circuit for digital video broadcasting over terrestrial (DVB-T) receivers. A step-down voltage regulator is utilized to suppress the coupled supply noise. A zero offset charge pump is employed to eliminate the static phase offset caused by the charge offset when the PLL is in lock. The measurement results on silicon using the TSMC (Taiwan Semiconductor Manufacturing Company) [email protected] 2P4M CMOS process show that the proposed PLL achieves as low as 72.7ps p2p jitter on silicon when the output frequency is 80MHz and the power consumption is merely 10.5mW given a 3.3V power supply.