100 results on '"Gai, Weixin"'
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2. 56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology
3. Equal-slope baud-rate CDR algorithm with optimized eye opening
4. The Impact of CTLE Poles on Receiver Eye Diagrams
5. A Dual-Core Digitally Controlled Oscillator with a Switched Capacitor
6. Adaptive Resistance Calibration Circuit for High-speed Serial Transceivers
7. A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS
8. 6.7 A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS
9. 6.3 A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS
10. A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS
11. A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS
12. A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS
13. A Delay Matching Technique for Relative Deterministic Jitter Reduction in 28GHz ADPLL
14. An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC
15. A Clock Delivery Path with Peaking Buffers for 112Gb/s Wireline Transceiver
16. A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications
17. Closed-Loop Diabetes Minipatch Based on a Biosensor and an Electroosmotic Pump on Hollow Biodegradable Microneedles
18. A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS
19. A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS
20. An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology
21. A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS
22. A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET
23. A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer
24. Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver
25. A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems
26. Pin‐efficient 9‐bit 8‐wire 4‐level synergetic‐equalisation coding scheme for 216 Gb/s PAM4 transceiver
27. Wearable Tape-Based Smart Biosensing Systems for Lactate and Glucose
28. Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop
29. A 10GHz Class-C Digitally-Controlled Oscillator with Fast Start-up Dynamic Biasing
30. A Statistics-Based Background Timing Skew Calibration Algorithm for Time-Interleaved ADCs
31. Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs
32. An 8–12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation
33. Hardware‐efficient slope‐error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver
34. 40 Gbps 4‐level pulse amplitude modulation closed‐loop decision‐feedback equaliser with high‐speed comparator in 55 nm CMOS technology
35. A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor
36. An 8.52–11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor
37. A 108fsrms 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching
38. A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS
39. A novel digital loop filter with frequency error prediction for fast-locking bang-bang ADPLL
40. 5-bit 100MHz two-phase delay-line based ADC for DC-DC converter
41. A low-power area-efficient wide-range offset calibration technique for high-speed high-resolution comparator
42. A clock-feedthrough compensation technique for bootstrapped switch
43. A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery
44. A 10GHz analogphase interpolator based on a novel quadrature clock generator
45. A 6.5-GHz digitally-controlled oscillatorwith supply sensitivity of 0.0071%-fDCO/1%-VDD
46. A speculative clock and data recovery architecture for multi-gigabit/s series links
47. A 1.27mW 20Gbps 1:16 DEMUX with a symmetrical-edge-delay sense amplifier
48. PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer
49. Swing‐programmable SST transmitter with power‐efficient de‐emphasis
50. A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis
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