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Two significant trends can be nowadays seen in automotive and industrial applications: an increase of the amount of data that is stored and elaborated by those systems, thus requiring bigger on-board DRAMs (Dynamic Random Access Memories), and the strict demands for reliability and safety. Safety is ruled by standards, that impose requirements for acceptable FIT rate–one of the most common metrics used for quantitatively evaluating the effects of such errors. It is then relevant to investigate the errors that can occur in DRAMs and propose mitigation techniques to deal with them. In this paper, die-to-die testing scenario is considered, and a methodology is described for mitigating the effects of errors by using well-known Error Correcting Codes (ECC). An advanced ECC solution is then presented along with the infrastructure needed for effectively testing DRAMs, including soft errors and permanent faults. The FIT rates calculations are finally considered, together with examples and case studies illustrating the effectiveness of the proposed solution.

This paper considers the reliability and safety issues in automotive applications which are of highest importance. FIT rate is one of the most common metrics used for quantitatively evaluating such issues. Strict requirements exist for acceptable FIT Rate in automotive applications. The problem of calculating the FIT rate at SoC level is considered in this paper and then it focuses on memories, which comprise a large part of current SoCs and have a great impact on the overall FIT rate. The vulnerability factors are considered, which help to get a better approximation of real-life situations. A methodology is presented for mitigating the effects of soft errors in memories via selective adoption of error detecting and correcting codes (ECC). Ways to calculate the FIT rate in the presence of ECC are considered and an advanced ECC solution is presented. Since using ECC increases the SoC area (extra logic and memory bits are needed) and decreases performance (delay in ECC logic that calculates / verifies the codes), a planning solution for choosing which memories should have ECC for optimal reliability/area is presented. Some experimental results are adduced to illustrate the effectiveness of the proposed techniques.

This innovative practice session includes three presentations which discuss test and reliability issues and solutions for external and embedded memories. At speed test for external memories, memory array diagnosis and interconnect faults detection, as well as the peculiarities of supporting different memory IPs including DRAM and HBM2 are among the topics discussed. As for embedded memories, FIT rate calculation and mitigation methodology is presented which is shown to be critical for automotive SoCs.

The fast growing Automotive SoC market presents new test challenges, combining traditional production requirements as well as new Functional Safety (FuSa) related aspects. In order to meet these challenges, an innovative approach must be introduced. This paper presents a detailed case study demonstrating typical Automotive SoC requirements, in addition to an advanced Uniformed Test Approach, specially tailored in order to fulfill them.

Given the fast growing complexity and miniaturization of automotive SoCs, this paper presents functional safety challenges and related solutions for such SoCs. The paper is based on ISO 26262 standard and shows experimental results on a SoC example to demonstrate the advantages of the proposed solutions.

The modern automotive industry has entered an era where the tendencies are towards increased automation and connectivity. With every new generation, the proportion of electronics-controlled systems in the vehicles is steadily growing. In parallel the safety and reliability requirements to automobiles are becoming more stringent thus requiring more sophisticated approaches. The problem is complicated by the fact that automotive has started to use cutting-edge technologies whose maturity might not be always at high level. Thus, there is a need to ensure not only low DPPM during production mode but also high reliability during mission mode. This paper presents an advanced Error Correcting Codes (ECC) solution which ensures high level of single-bit and multi-bit error detection and correction for memories operating in mission mode. This solution addresses the main requirements posed by automotive industry as well as successfully passed ISO 26262 certification with ASIL-D grade.

New ultra-deep submicron technologies are bringing not only new advantages such extraordinary transistor densities or unforeseen performances, but also new uncertainties such soft-error susceptibility, modelling complexity, coupling effects, leakage contribution and increased sensitivity to internal and external disturbs. Nowadays, embedded memories are taking profit of such new technologies and they are more and more used in systems: therefore as robustness and reliability requirement increase, memory systems must be protected against different kind of faults (permanent and transient) and that should be done in an efficient way. It means that reliability and costs, such overhead and performance degradation, must be efficiently tuned based on the system and on the application. Moreover, the new emerging norms for safety-critical applications such IEC 61508 are requiring precise answers in terms of robustness also in the case of memory systems. In this paper, classical protection techniques for error detection and correction are enriched with a system-aware approach, where the memory system is analyzed based on its role in the application. A configurable memory protection system is presented, together with the results of its application to a proof-of-concept architecture. This work has been developed in the framework of MEDEA+ T126 project called BLUEBERRIES.